73S8009C Data Sheet
DS_8009C_025
3.9 I/O Circuitry and Timing
The states of the I/O, AUX1, and AUX2 pins are low after power on reset and they are in high when the
activation sequencer turns on the I/O reception state. See the Activation and De-activation Sequence
section for more details on when the I/O reception is enabled. The states of I/OUC, AUX1UC, and
AUX2UC are high after power on reset.
Within a card session and when the I/O reception state is turned on, the first I/O line on which a falling
edge is detected becomes the input I/O line and the other becomes the output I/O line. When the input
I/O line rising edge is detected, then both I/O lines return to their neutral state. Figure 10 shows the state
diagram of how the I/O and I/OUC lines are managed to become input or output.
Neutral
State
No
I/O
reception
Yes
I/O
&
not I/OUC
No
Yes
I/OUC
&
No
not I/O
Yes
I/OUC
in
I/OICC
in
No
No
I/OUC
yes
I/O
yes
Figure 10: I/O and I/OUC State Diagram
24
Rev. 1.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
