DS_1215F_003
73S1215F Data Sheet
The USB interface includes a Serial Interface Engine (SIE) that handles NRZI encoding/decoding, bit
stuffing / unstuffing, and CRC generation/checking. It also generates headers for packets to be
transmitted and decodes the headers of received packets. An analog transceiver interfaces with the
external USB bus. The USB interface hardware performs error checking and removes the USB protocol
fields from the incoming messages before passing the data to the firmware. The hardware also adds the
USB protocol fields to the outgoing messages coming from the firmware. The hardware implements
NRZI encoding/decoding, CRC checking/generation (both on data and token packets), device address
decoding, handshake packet generation, Data0/Data1 toggle synchronization, bit stuffing, bus idle
detection and other protocol generation/checking required in Chapter 8 of the Universal Serial Bus
Specification, Revision 2.0.
The firmware is responsible for servicing and building of the messages required under Chapter 9 of the
Universal Serial Bus Specification, Revision 2.0. Device configuration is stored in the firmware. Data
received from the USB port is stored in the appropriate IN FIFO that is read by the firmware and
processed. The messages to be sent back to the USB host are generated by firmware and placed back
into the appropriate OUT FIFO. Stall/NAK handshakes are generated as appropriate if the RAM is not
available for another message from the USB host. Suspend and resume modes are supported. All
register/FIFO spaces are located in Data Memory space. The FIFOs are dedicated for USB storage and
are unused in a configuration that is not using USB. All registers in the USB interface are located in
external data memory address (XRAM) space starting at address FC00’h.
Rev. 1.4
73
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
