DS_1215F_003
73S1215F Data Sheet
Table 5: Program Security Registers
Description
Register
SFR
R/W
Address
FLSHCTL
0xB2
R/W Bit 0 (FLSH_PWE): Program Write Enable:
0 – MOVX commands refer to XRAM Space, normal operation (default).
1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.
This bit is automatically reset after each byte written to flash. Writes to
this bit are inhibited when interrupts are enabled.
W
Bit 1 (FLSH_MEEN): Mass Erase Enable:
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
R/W Bit 6 (SECURE):
Enables security provisions that prevent external reading of flash
memory and CE program RAM. This bit is reset on chip reset and may
only be set. Attempts to write zero are ignored.
TRIMPCtl
FUSECtl
SECReg
0xFFD1
0xFFD2
0xFFD7
W
W
W
0xA6 value will cause the selected fuse to be blown. All other values
will stop the burning process.
0x54 value will set up for security fuse control. All other values are
reserved and should not be used.
Bit 7 (PARAMSEC):
0 – Normal operation.
1 – Enable permanent programming of the security fuses.
R
Bit 5 (SECPIN):
Indicates the state of the SEC pin. The SEC pin is held low by a pull-
down resistor. The user can force this pin high during boot sequence
time to indicate to firmware that sec mode 1 is desired.
R/W Bit 1 (SECSET1):
See the Program Security section.
R/W Bit 0 (SECSET0):
See the Program Security section.
Rev. 1.4
17
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
