DS_1215F_003
73S1215F Data Sheet
1.4
12/16/2008
In Table 1, added more description to the VCC, VPC, VDD, SCL, SDA,
PRES, SEC and TEST pins.
In Section 1.3.2, changed “FLSH_ERASE” to “ERASE” and
“FLSH_PGADR” to “PGADDR”. Added “The PGADDR register denotes
the page address for page erase. The page size is 512 (200h) bytes and
there are 128 pages within the flash memory. The PGADDR denotes the
upper seven bits of the flash memory address such that bit 7:1 of the
PGADDR corresponds to bit 15:9 of the flash memory address. Bit 0 of
the PGADDR is not used and is ignored.” In the description of the
PGADDR register, added “Note: the page address is shifted left by one bit
(see detailed description above).”
Changed the register address for ATRMsB from FE21 to FE1F.
In Table 5, changed “FLSHCRL” to “FLSHCTL”.
In Table 5, moved the TRIMPCtl bit description to FUSECtl and moved the
FUSECtl bit description to TRIMPCtl.
In Table 6, changed “PGADR” to “PGADDR”.
In Table 7, added PGADDR.
In Table 8, changed the reset value for RTCCtl from “0x81” to “0x00”.
Added the RTCTrim0 and ACOMP registers. Deleted the OMP, VRCtl,
LEDCal and LOCKCtl registers.
In Table 23, corrected the descriptions for TCON.2 and TCON.0.
In Table 62, added “Write data controls output level of pin LEDn. Read will
report level of pin LEDn.” to the description of LEDD3, LEDD2 and
LEDD1.
In Section 1.7.15.5 (number 3), deleted “If CLKOFF/SCLKOFF is high and
SYCKST is set=1(STXCtl, b7=1), Rlen=max will stop the clock at the
selected (CLKLVL or SCLKLVL) level.”
In Section 1.7.15.5, added “Synchronous card operation is broken down
into three primary types. These are commonly referred to as 2-wire,
3-wire and I2C synchronous cards. Each card type requires different
control and timing and therefore requires different algorithms to access.
Teridian has created an application note to provide detailed algorithms for
each card type. Refer to the application note titled 73S12xxF
Synchronous Card Design Application Note.”
In the VccVtl.0 bit description, deleted “When in power down mode, VDD
0V. VDD can only be turned on by pressing the ON/OFF switch or by
=
application of 5V to VBUS. If VBUS power is available and SCPWRDN bit is
set, it has no effect until VBUS is removed and VDD will shut off.”
In Table 86 and Table 117, changed the SYCKST bit to I2CMODE.
In Figure 26, replaced the schematic with a new schematic.
Added Section 6, Ordering Information.
Added Section 7, Related Documentation.
Added Section 8, Contact Information.
Formatted the document per new standard. Added section numbering.
Rev. 1.4
135
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
