73S1210F Data Sheet
DS_1210F_001
Timer/Counter Control Register (TCON): 0x88 0x00
Table 22: The TCON Register
MSB
TF1
LSB
IT0
TR1
TF0
TR0
IE1
IT1
IE0
Bit
Symbol
Function
TCON.7
TCON.6
TCON.5
TCON.4
TCON.3
TF1
TR1
TF0
TR0
IE1
Timer 1 overflow flag.
Not used for interrupt control.
Timer 0 overflow flag.
Not used for interrupt control.
Interrupt 1 edge flag is set by hardware when the falling edge on external
interrupt int1 is observed. Cleared when an interrupt is processed.
TCON.2
TCON.1
TCON.0
IT1
IE0
IT0
Interrupt 1 type control bit. 1 selects falling edge and 0 selects low level for
input pin to cause an interrupt.
Interrupt 0 edge flag is set by hardware when the falling edge on external
interrupt int0 is observed. Cleared when an interrupt is processed.
Interrupt 0 type control bit. 1 selects falling edge and 0 sets low level for input
pin to cause interrupt.
Timer/Interrupt 2 Control Register (T2CON): 0xC8 0x00
Table 23: The T2CON Register
MSB
LSB
–
I3FR
I2FR
–
–
–
–
–
Bit
Symbol
Function
T2CON.7
–
External interrupt 3 failing/rising edge flag.
T2CON.6
T2CON.5
I3FR
I3FR = 0 external interrupt 3 negative transition active.
I3FR = 1 external interrupt 3 positive transition active.
External interrupt 3 failing/rising edge flag.
I2FR
I2FR = 0 external interrupt 3 negative transition active.
I2FR = 1 external interrupt 3 positive transition active.
T2CON.4
T2CON.3
T2CON.2
T2CON.1
T2CON.0
–
–
–
–
–
36
Rev. 1.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
