73S1210F Data Sheet
DS_1210F_001
START Bit
CLK
IO
Data from Card -end of ATR
Data from TX FIFO
6
RLength
Count MAX
RLen=0
Rlen=1
RLength Count - was set for length of ATR
5
1
2
RLength Interrupt
CLK Stop
3
CLK Stop Level
IO Bit
7
IODir Bit
6
TX/RX Mode Bit
TX = '1'
4
1. Interrupt generated when Rlength counter is MAX.
2. Read and clear Interrupt.
3. Set CLK Stop and CLK Stop level high in Interrupt routine.
4. Set TX/RX Bit to TX mode.
5. Reload Rlength Counter.
6. Set IO Bit low and IODir = Output. Since Rlen=(MAX or 0) and TX/RX =1, IO pin is controlled by IO bit.
7. Clear CLK Stop and CLK Stop level.
Note: Data in TX fifo should not be Empty here.
Synchronous Clock Start/Stop Mode style Start bit procedure. This procedure should be used to
generate the start bit insertion in Synchronous mode for Synchronous Clock Start/Stop Mode protocol.
Figure 22: Creation of Synchronous Clock Start/Stop Mode Start Bit in Sync Mode
CLK
I2CMode = 1: Data to/from Card
I2CMode = 0: Data from TX fifo
I2CMode = 1:ACK Bit (to/from card)
I2CMode = 0: Data from TX fifo
IO
6
RLength Count MAX
2
RLength Count
(Rlength = 9)
STOP Bit
1
RLength Interrupt
CLK Stop
8
3
CLK Stop Level
IO Bit
7
4
IODir Bit
TX/RX Mode Bit
TX = '1'
5
TX/RX mode
1. Interrupt generated when Rlength counter is MAX.
2. Read and clear Interrupt.
3. Set CLK Stop and CLK Stop level high.
4. Set IO Bit low and IODir = Output.
5. Set TX/RX Bit to TX mode.
6. Reload Rlength Counter.
7. Set IO Bit High and IODir = Output.
8. Clear CLK Stop and CLK Stop level.
Note: Data in TX fifo should not be Empty here.
Synchronous Clock Start/Stop Mode Stop bit procedure. This procedure should be used to
generate the Stop bit in Synchronous Mode. SYCKST is bit 7 of STXCTL register.
Figure 23: Creation of Synchronous Clock Start/Stop Mode Stop Bit in Sync Mode
78
Rev. 1.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
