DS_1210F_001
73S1210F Data Sheet
Miscellaneous Control Register 1 (MISCtl1): 0xFFF2 0x10
Table 16: The MISCtl1 Register
MSB
LSB
–
–
–
FRPEN FLSH66
–
–
–
Bit
Symbol
Function
MISCtl1.7
MISCtl1.6
–
–
Flash Read Pulse enable (low). If FRPEN = 1, the Flash Read signal is
passed through with no change. When FRPEN = 0 a one-shot circuit that
shortens the Flash Read signal is enabled to save power. The Flash Read
pulse will shorten to 40 or 66ns (approximate based on the setting of the
FLSH66 bit) in duration, regardless of the MPU clock rate. For MPU clock
frequencies greater than 10MHz, this bit should be set high.
MISCtl1.5
FRPEN
When high, creates a 66ns Flash read pulse, otherwise creates a 40ns
read pulse when FRPEN is set.
MISCtl1.4
FLSH66
MISCtl1.3
MISCtl1.2
MISCtl1.1
MISCtl1.0
–
–
–
–
Master Clock Control Register (MCLKCtl): 0x8F 0x0A
Table 17: The MCLKCtl Register
MSB
LSB
MCT.2 MCT.1 MCT.0
HSOEN KBEN
SCEN
–
–
Bit
Symbol
Function
High-speed oscillator enable. When set = 1, disables the high-speed
crystal oscillator and VCO/PLL system. This bit is not changed when the
PWRDN bit is set but the oscillator/VCO/PLL is disabled.
MCLKCtl.7
MCLKCtl.6
MCLKCtl.5
HSOEN*
KBEN
1 = Disable the keypad logic clock. This bit is not changed in PWRDN
mode but the function is disabled.
1 = Disable the smart card logic clock. This bit is not changed in PWRDN
mode but the function is disabled. Interrupt logic for card insertion/removal
remains operable even with smart card clock disabled.
SCEN
MCLKCtl.4
MCLKCtl.3
MCLKCtl.2
MCLKCtl.1
–
–
MCT.2
MCT.1
This value determines the ratio of the VCO frequency (MCLK) to the
high-speed crystal oscillator frequency such that:
MCLK = (MCount*2 + 4)*Fxtal. The default value is MCount = 2h such
that MCLK = (2*2 + 4)*12.00MHz = 96MHz.
MCLKCtl.0
MCT.0
*Note: The HSOEN bit should never be set under normal circumstances. Power down control should
only be initiated via use of the PWRDN bit in MISCtl0.
Rev. 1.4
31
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
