73S1210F Data Sheet
DS_1210F_001
External Interrupt Control Register (INT5Ctl): 0xFF94 0x00
Table 14: The INT5Ctl Register
MSB
LSB
KPIEN KPINT
PDMUX
–
–
–
–
–
Bit
Symbol
Function
When set = 1, enables interrupts from Keypad (normally going to int5),
Smart Card interrupts (normally going to int4), or USR(7:0) pins (int0) to
cause interrupt on int0. The assertion of the interrupt to int0 is delayed by
512 MPU clocks to allow the analog circuits, including the clock system, to
stabilize. This bit must be set prior to asserting the PWRDN bit in order to
properly configure the interrupts that will wake up the circuit. This bit is
reset = 0 when this register is read.
INT5Ctl.7
PDMUX
INT5Ctl.6
INT5Ctl.5
INT5Ctl.4
INT5Ctl.3
INT5Ctl.2
INT5Ctl.1
INT5Ctl.0
–
–
–
–
–
KPIEN
KPINT
Keypad interrupt enable.
Keypad interrupt flag.
Miscellaneous Control Register 0 (MISCtl0): 0xFFF1 0x00
Table 15: The MISCtl0 Register
MSB
LSB
SLPBK SSEL
PWRDN
–
–
–
–
–
Bit
Symbol
Function
This bit sets the circuit into a low-power condition. All analog (high-speed
oscillator and VCO/PLL) functions are disabled 32 MPU clock cycles after
this bit is set = 1. This allows time for the next instruction to set the STOP
bit in the PCON register to stop the CPU core. The MPU is not operative in
this mode. When set, this bit overrides the individual control bits that
otherwise control power consumption.
MISCtl0.7
PWRDN
MISCtl0.6
MISCtl0.5
MISCtl0.4
MISCtl0.3
MISCtl0.2
MISCtl0.1
MISCtl0.0
–
–
–
–
–
SLPBK
SSEL
UART loop back testing mode.
Serial port pins select.
30
Rev. 1.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
