DS_1210F_001
73S1210F Data Sheet
Symbol
Parameter
Condition
Min
Typ.
Max
Unit
Interface Requirements – Data Signals: I/O, AUX1 and AUX2
IOH = 0
0.9 * VCC
0.75 VCC
VCC+0.1
VCC+0.1
0.15 *VCC
VCC+0.30
0.2 * VCC
0.1
V
V
VOH
Output level, high
IOH = -40µA
VOL
VIH
VIL
Output level, low
Input level, high
Input level, low
IOL = 1mA
V
0.6 * VCC
-0.15
V
V
IOL = 0
IOL = 1mA
VIH = VCC
VIL = 0
V
Output voltage when outside
of session
VINACT
0.3
V
ILEAK
IIL
Input leakage
10
µA
mA
mA
Input current, low
Input current, low
0.65
IIL
VIL = 0
0.7
For output low, shorted
to VCC through 33Ω
ISHORTL
Short circuit output current
15
mA
For output high,
shorted to ground
through 33Ω
ISHORTH
Short circuit output current
15
mA
For I/O, AUX1, AUX2,
CL = 80pF, 10% to
tR, tF
Output rise time, fall times
90%. For I/OUC,
100
ns
AUX1UC, AUX2UC, CL
= 50Pf, 10% to 90%.
tIR, tIF
RPU
Input rise, fall times
Internal pull-up resistor
Maximum data rate
1
14
1
µs
kΩ
Output stable for
>200ns
8
11
FDMAX
MHz
Reset and Clock for card interface, RST, CLK
VOH
VOL
Output level, high
Output level, low
0.9 * VCC
0
VCC
0.15 *VCC
0.1
V
V
V
V
IOH = -200µA
IOL= 200µA
IOL = 0
Output voltage when outside
of session
VINACT
IOL = 1mA
0.3
IRST_LIM
ICLK_LIM
Output current limit, RST
Output current limit, CLK
30
70
8
mA
ns
CL = 35pF for CLK,
10% to 90%
tR, tF
Output rise time, fall time
Duty cycle for CLK
CL = 200pF for RST,
10% to 90%
100
55
ns
%
CL = 35pF, FCLK
45
δ
≤ 20MHz, CLKIN duty
cycle is 48% to 52%.
Rev. 1.4
109
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
