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73S1210F-44IM/F 参数 Datasheet PDF下载

73S1210F-44IM/F图片预览
型号: 73S1210F-44IM/F
PDF下载: 下载PDF文件 查看货源
内容描述: 自包含智能卡读卡器与密码键盘和电源管理 [Self-Contained Smart Card Reader with PINpad and Power Management]
分类和应用: 微控制器和处理器外围集成电路uCs集成电路uPs集成电路
文件页数/大小: 126 页 / 1200 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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DS_1210F_001  
73S1210F Data Sheet  
Smart Card Interrupt Register (SCInt): 0xFE01 0x00  
When the smart card interrupt is asserted, the firmware can read this register to determine the actual  
cause of the interrupt. The bits are cleared when this register is read. Each interrupt can be disabled by  
the Smart Card Interrupt Enable register. Error processing must be handled by the firmware. This  
register relates to the interface that is active – see the SCSel register (above).  
Table 73: The SCInt Register  
MSB  
LSB  
WAITTO CRDEVT VCCTMRI RXDAV TXEVT TXSENT TXERR RXERR  
Bit  
Symbol  
Function  
Wait Timeout - An ATR or card wait timeout has occurred. In sync mode,  
this interrupt is asserted when the RLen counter (it advances on falling  
edges of CLK/ETU) reaches the loaded (max) value. This bit is cleared  
when the SCInt register is read. When running in Synchronous Clock  
Stop Mode, this bit becomes RLenINT interrupt (set when the Rlen  
counter reaches the terminal count).  
SCInt.7  
WAITTO  
Card Event - A card event is signaled via pin DETCARD either when the  
Card was inserted or removed (read the CRDCtl register to determine  
card presence) or there was a fault condition in the interface circuitry.  
This bit is functional even if the smart card logic clock is disabled and  
when the PWRDN bit is set. This bit is cleared when the SCInt register is  
read.  
SCInt.6  
SCInt.5  
SCInt.4  
CRDEVT  
VCCTMRI  
RXDAV  
VCC Timer - This bit is set when the VCCTMR times out. This bit is  
cleared when the SCInt register is read.  
Rx Data Available - Data was received from the smart card because the  
Rx FIFO is not empty. In bypass mode, this interrupt is generated on a  
falling edge of the smart card I/O line. After receiving this interrupt in  
bypass mode, firmware should disable it until the firmware has received  
the entire byte and is waiting for the next start delimiter. This bit is  
cleared when there is no RX data available in the RX FIFO.  
TX Event - Set whenever the TXEMTY or TXFULL bits are set in the  
SRXCtl SFR. This bit is cleared when the STXCtl register is read.  
SCInt.3  
SCInt.2  
TXEVNT  
TXSENT  
TX Sent - Set whenever the ISO UART has successfully transmitted a  
byte to the smart card. Also set when a CRC/LRC byte is sent in T=1  
mode. Will not be set in T=0 when a break is detected at the end of a  
byte (when break detection is enabled). This bit is cleared when the  
SCInt register is read.  
TX Error - An error was detected during the transmission of data to the  
smart card as indicated by either BREAKD or TXUNDR bit being set in  
the STXCtl SFR. Additional information can be found in that register  
description. This bit is cleared when the STXCtl register is read.  
SCInt.1  
SCInt.0  
TXERR  
RXERR  
RX Error - An error was detected during the reception of data from the  
smart card. Additional information can be found in the SRXCtl register.  
This interrupt will be asserted for RXOVRR, or RX Parity error events.  
This bit is cleared when the SRXCtl register is read.  
Rev. 1.4  
81