73S1210F Data Sheet
DS_1210F_001
All ports on the chip are bi-directional. Each consists of a Latch (SFR ‘USR70’), an output driver, and an
input buffer, therefore the MPU can output or read data through any of these ports if they are not used for
alternate purposes.
1.6 Instruction Set
All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set
and of the associated op-codes is contained in the 73S12xxF Software User’s Guide.
1.7 Peripheral Descriptions
1.7.1 Oscillator and Clock Generation
The 73S1210F has one oscillator circuit for the main CPU clock. The main oscillator circuit is designed to
operate with various crystal or external clock frequencies. An internal divider working in conjunction with a
PLL and VCO provides a 96MHz internal clock within the 73S1210F. 96 MHz is the recommended
frequency for proper operation of specific peripheral blocks such as the specific timers, ISO 7816 UART
and interfaces, Step-up converter, and keypad. The clock generation and control circuits are shown in
Figure 3.
MCount(2:0)
M DIVIDER
12.00MHz
/(2*N + 4)
KEYCLK
1kHz
DIVIDER
/93760
HOSCen
MCLK
96MHz
X12IN
Phase
Freq
DET
HIGH
XTAL
OSC
VCO
HCLK
12.00MHz
X12OUT
CPU CLOCK
DIVIDER
6 bits
1.5-48MHz
7.386MHz
ICLK
7.386MHz
CPUCKDiv
MPU CLOCK - CPCLK
3.6923MHz
I2CCLK
DIVIDE
by 120
400kHz
I2C_2x
800kHz
CLK1M
DIVIDE
by 96
1MHz
SMART CARD LOGIC
BLOCK CLOCK
SCCLK
SC/SCE
CLOCK
Prescaler 6bits
SEL
ETU CLOCK
ETUCLK
SCECLK
SCLK
CLOCK
Prescaler 6bits
DIVIDER
12 bits
SELSC
See SC Clock descriptions for more accurate diagram
SCCKenb
Figure 3: Clock Generation and Control Circuits
22
Rev. 1.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
