73S1210F Data Sheet
DS_1210F_001
In Section 1.7.15.5, deleted “The ETU clock is held in reset condition until
the activation sequence begins (either by VCCOK=1 or VCCTMR timeout)
and will go high ½ the ETU period thereafter.”
In Section 1.7.15.5, added “Synchronous card operation is broken down
into three primary types. These are commonly referred to as 2-wire,
3-wire and I2C synchronous cards. Each card type requires different
control and timing and therefore requires different algorithms to access.
Teridian has created an application note to provide detailed algorithms for
each card type. Refer to the application note titled 73S12xxF
Synchronous Card Design Application Note.”
In Table 78 and Table 107, changed the SYCKST bit to I2CMODE.
In Figure 25, replaced the schematic with a new schematic.
In Section 3.4, changed the Fxtal Min from 4 to 6.
Added 44-pin QFN package.
Added Section 8, Related Documentation.
Added Section 9, Contact Information.
Formatted the document per new standard. Added section numbering.
1.3
1.4
1/22/2009
5/12/2009
Changed the value for the IDD_IN Power Down (25°C) parameter from 13
µA to 15 µA.
In Table 1, corrected the 44 QFN GND pin from 37 to 26.
Added the “with Programming” ordering numbers to Table 109.
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Rev. 1.4
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