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73S1210F-44IM/F 参数 Datasheet PDF下载

73S1210F-44IM/F图片预览
型号: 73S1210F-44IM/F
PDF下载: 下载PDF文件 查看货源
内容描述: 自包含智能卡读卡器与密码键盘和电源管理 [Self-Contained Smart Card Reader with PINpad and Power Management]
分类和应用: 微控制器和处理器外围集成电路uCs集成电路uPs集成电路
文件页数/大小: 126 页 / 1200 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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DS_1210F_001  
73S1210F Data Sheet  
ATR Timeout Registers (ATRLsB): 0xFE20 0x00, (ATRMsB): 0xFE1F 0x00  
These registers form the ATR timeout (ATRTO [15:0]) parameter. Time in ETU between the leading  
edge of the first character and leading edge of the last character of the ATR response. Timer is enabled  
when the RCVATR is set and starts when leading edge of the first start bit is received and disabled when  
the RCVATR is cleared. An ATR timeout is generated if this time is exceeded.  
Table 103: The ATRLsB Register  
MSB  
ATRTO.7  
LSB  
ATRTO.6  
ATRTO.5  
ATRTO.4  
ATRTO.3  
ATRTO.1 ATRTO.2 ATRTO.0  
Table 104: The ATRMsB Register  
MSB  
LSB  
ATRTO.15 ATRTO.14 ATRTO.13 ATRTO.12 ATRTO.11 ATRTO.10 ATRTO.9 ATRTO.8  
TS Timeout Register (STSTO): 0xFE21 0x00  
The TS timeout is the time in ETU between the de-assertion of smart card reset and the leading edge of  
the TS character in the ATR (when DETTS is set). The timer is started when smart card reset is  
de-asserted. An ATR timeout is generated if this time is exceeded (MUTE card).  
Table 105: The STSTO Register  
MSB  
TST0.7  
LSB  
TST0.0  
TST0.6  
TST0.5  
TST0.4  
TST0.3  
TST0.1  
TST0.2  
Reset Time Register (RLength): 0xFE22 0x70  
Time in ETUs that the hardware delays the de-assertion of RST. If set to 0 and RSTCRD = 0, the hardware  
adds no extra delay and the hardware will release RST after VCCOK is asserted during power-up. If set to 1,  
it will delay the release of RST by the time in this register. When the firmware sets the RSTCRD bit, the  
hardware will assert reset (RST = 0 on pin). When firmware clears the bit, the hardware will release RST  
after the delay specified in Rlen. If firmware sets the RSTCRD bit prior to instructing the power to be applied  
to the smart card, the hardware will not release RST after power-up until RLen after the firmware clears the  
RSTCRD bit. This provides a means to power up the smart card and hold it in reset until the firmware wants  
to release the RST to the selected smart card. Works with the selected smart card interface.  
Table 106: The RLength Register  
MSB  
RLen.7  
LSB  
RLen.0  
RLen.6  
RLen.5  
RLen.4  
RLen.3  
RLen.1  
RLen.2  
Rev. 1.4  
101