DS_1209F_004
73S1209F Data Sheet
Table 3: Flash Special Function Registers
R/W Description
Register
SFR
Address
ERASE
0x94
W
This register is used to initiate either the Flash Mass Erase cycle or the
Flash Page Erase cycle. Specific patterns are expected for ERASE in
order to initiate the appropriate Erase cycle (default = 0x00).
0x55 – Initiate Flash Page Erase cycle. Must be proceeded by a write to
PGADDR @ SFR 0xB7.
0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a write
to FLSH_MEEN @ SFR 0xB2 and the debug port must be enabled.
Any other pattern written to ERASE will have no effect.
PGADDR
FLSHCTL
0xB7
0xB2
R/W Flash Page Erase Address register containing the flash memory page
address (page 0 through 127) that will be erased during the Page Erase
cycle (default = 0x00). Note: the page address is shifted left by one bit
(see detailed description above).
Must be re-written for each new Page Erase cycle.
R/W Bit 0 (FLSH_PWE): Program Write Enable:
0 – MOVX commands refer to XRAM Space, normal operation (default).
1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.
This bit is automatically reset after each byte written to flash. Writes to
this bit are inhibited when interrupts are enabled.
W
Bit 1 (FLSH_MEEN): Mass Erase Enable:
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
R/W Bit 6 (SECURE):
Enables security provisions that prevent external reading of flash
memory and CE program RAM. This bit is reset on chip reset and may
only be set. Attempts to write zero are ignored.
Rev. 1.2
13
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