73S1209F Data Sheet
DS_1209F_004
Symbol
Parameter
Condition
Min
Typ.
Max
Unit
Interface Requirements – Data Signals: I/O, AUX1 and AUX2.
IOH =0
0.9 * VCC
0.75 VCC
VCC+0.1
VCC+0.1
V
V
Output level, high (I/O,
AUX1, AUX2)
VOH
IOH = -40μA
Output level, low (I/O, AUX1,
AUX2)
0.15 *VCC
VCC+0.30
0.2 * VCC
VOL
VIH
VIL
IOL=1mA
V
V
V
Input level, high (I/O, AUX1,
AUX2)
0.6 * VCC
-0.15
Input level, low (I/O, AUX1,
AUX2)
IOL = 0
0.1
0.3
10
V
V
Output voltage when outside
of session
VINACT
IOL = 1mA
VIH = VCC
ILEAK
IIL
ISHORTL
Input leakage
μA
Input current, low (I/O, AUX1,
AUX2)
VIL = 0
0.65
15
mA
mA
For output low, shorted
to VCC through 33Ω
Short circuit output current
For output high,
shorted to ground
through 33Ω
ISHORTH
Short circuit output current
15
mA
ns
For I/O, AUX1, AUX2,
CL = 80pF, 10% to
90%.
tR, tF
Output rise time, fall times
100
tIR, tIF
RPU
Input rise, fall times
Internal pull-up resistor
Maximum data rate
1
14
1
μs
kΩ
Output stable for
>200ns
8
11
FDMAX
MHz
Reset and Clock for Card Interface, RST, CLK
VOH
VOL
Output level, high
Output level, low
0.9 * VCC
0
VCC
0.15 *VCC
0.1
V
V
V
V
IOH =-200μA
IOL=200μA
IOL = 0
Output voltage when outside
of session
VINACT
IOL = 1mA
0.3
IRST_LIM
Output current limit, RST
30
70
ICLK_LIM
Output current limit, CLK
CLK slew rate
mA
V/ns
V/ns
CLKSR3V
CLKSR5V
VCC = 3V
VCC = 5V
0.3
0.5
CLK slew rate
CL = 35pF for CLK,
10% to 90%
8
ns
ns
tR, tF
Output rise time, fall time
Duty cycle for CLK
CL = 200pF for RST,
10% to 90%
100
CL =35pF,
45
55
%
δ
FCLK ≤ 20MHz
108
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
