DS_1209F_004
73S1209F Data Sheet
Pin (68 QFN)
Pin (44 QFN)
Pin Name
Equivalent
Circuit*
Description
INT2
SIO
SCLK
PRES
52
50
48
64
32
31
30
43
Type
I
IO
O
I
General purpose interrupt input.
IO data signal for use with external Smart Card interface
circuit such as 73S8010.
Clock signal for use with external Smart Card interface
circuit.
Smart Card presence. Active high. Note: the pin has a
very weak pull down resistor. In noisy environments, an
external pull down may be desired to insure against a
false card event.
Smart Card presence. Active low. Note: the pin has a
very weak pull up resistor. In noisy environments, an
external pull up may be desired to insure against a false
card event.
Smart card clock signal.
Smart card Reset signal.
Smart card Data IO signal.
Auxiliary Smart Card IO signal (C4).
Auxiliary Smart Card IO signal (C8).
Smart Card VCC supply voltage output. A 0.47μF
capacitor is required and should be located at the smart
card connector. The capacitor should be a ceramic type
with low ESR.
Smart Card Ground.
Smart Card LDO regulator power supply source. A
10μF and a 0.1μF capacitor are required at the VPC
input. The 10μF capacitor should be a ceramic type
with low ESR.
PRESB
56
35
I
CLK
RST
IO
AUX1
AUX2
VCC
57
59
63
62
61
60
36
38
42
41
40
39
O
O
IO
IO
IO
PSO
GND
VPC
58
55
37
34
GND
PSI
TBUS(3:0)
0
1
2
3
RXTX
ERST
ISBR
TCLK
ANA_IN
SEC
TEST
IO
53
49
47
43
45
40
68
41
15
67
54
26
10
2
33
28
25
IO
IO
IO
I
AI
I
DI
Trace bus signals for ICE.
ICE control.
ICE control.
ICE control.
ICE control.
Analog input pin. This signal goes to a programmable
comparator and is used to sense the value of an
external voltage.
Input pin for use in programming security fuse. It should
be connected to ground when not in use.
Test pin, should be connected to ground.
Rev. 1.2
9
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
