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73M1922-IVTR/F 参数 Datasheet PDF下载

73M1922-IVTR/F图片预览
型号: 73M1922-IVTR/F
PDF下载: 下载PDF文件 查看货源
内容描述: [Consumer Circuit, PDSO20, ROHS COMPLIANT, MO-153AC, TSSOP-20]
分类和应用: 光电二极管商用集成电路
文件页数/大小: 82 页 / 1086 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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73M1822/73M1922 Data Sheet  
DS_1x22_017  
8.6 73M1x22 in Daisy Chain Configuration  
An internal register controls the daisy chain mode. FS pin of a slave device is an input from the FSD pin of  
the preceding device. In this arrangement, the HC bit (Register 0x02[0]) is ignored and the Software control is  
automatically enabled. Setting CTL (bit 0 of the SDIN data stream) to 1 does the control frame request. The  
delayed FS, FSD, is fed to the subsequent slave device as FS. FSD is delayed from FS and always 16 SCLK  
periods wide. There are 256 SCLK pulses between frame syncs. A maximum of 7 slaves can be supported.  
To aid the host in identifying the master data frame, the least significant bit of the 16-bit word (from SDOUT)  
from the master can be forced to “1” and the least significant bit of the 16-bit word from the slave(s) to “0”  
by controlling the MSID bits (Register 0x01[2]) of each device. In the cascade mode, the number of slaves  
supported must be specified in the NSLAVE bits (Register 0x01[6:4]).  
It is important to note that slave devices OSCIN comes from the SCLK pin of the Master device. If a device  
is configured as a Slave (M/S=0), the internal PLL is automatically programmed for the correct operation  
regardless of the external PLL programming. Figure 23 and Figure 24 illustrate the daisy chain  
configuration.  
MCLK  
OSCIN  
SCLK  
SDIN  
73M1902  
(Master)  
SCLK  
SDOUT  
SDIN  
SDOUT  
FS  
HOST  
"1"  
M/S  
FS  
"1"  
"1"  
TYPE  
FSD  
MODE  
OSCIN  
73M1822/  
73M1902  
SCLK  
SDIN  
(Slave0)  
SDOUT  
FS  
"0"  
M/S  
TYPE  
MODE  
"0"  
"x"  
FSD  
OSCIN  
73M1822/  
73M1902  
SCLK  
SDIN  
(Slave1)  
SDOUT  
FS  
"0"  
M/S  
"0"  
"x"  
TYPE  
FSD  
MODE  
Gray pins are optional depending on the package type.  
Figure 23: Daisy Chaining a Master and Two Slaves  
If requested by setting the CTL(bit0 of SDIN stream (Master))  
Data Frame  
Control Frame  
128 cycles of sclk  
128 cycles of sclk  
SCLK  
FS  
16 cycles of  
sclk  
FSD(Master)  
andFS(Slave0)  
16 cycles of  
sclk  
FSD(Slave0)  
and FS(Slave1)  
16 cycles of  
sclk  
16 cycles of  
sclk  
Figure 24: Timing Diagram with One Master and Two Slaves  
50  
Rev. 1.6