73M1903C-IMR/F 参数 Datasheet PDF下载

73M1903C

Modem Analog Front End

DATA SHEET

PIN DESCRIPTION

The TERIDIAN 73M1903C modem Analog Front End (AFE) IC is available in a 32 pin QFN package. The

following table describes the function of each pin. There are three pairs of power supply pins, VPA

(analog), VPD (digital) and VPPLL (PLL). They should be separately decoupled from the supply source

in order to isolate digital noise from the analog circuits internal to the chip. VPPLL can be directly

connected to VPD. Failure to adequately isolate and decouple these supplies will compromise device

performance.

PIN NAME

VND

VNA

VPD

VPA

VPPLL

VNPLL

TYPE

GND

GND

PWR

PWR

PWR

PWR

PIN #

1, 22

16

2, 25

9

20

17

DESCRIPTION

Negative Digital Ground

Negative Analog Ground

Positive Digital Supply

Positive Analog Supply

Positive PLL Supply, shared with VPD

Negative PLL Ground

Master reset. When this pin is a logic 0 all registers are reset to their

default states; Weak-pulled high-default. A low pulse longer than 100ns

is needed to reset the device. The device will be ready within 100us after

this pin goes to logic 1 state.

Crystal oscillator input. When providing an external clock source, drive

OSCIN.

Crystal oscillator circuit output pin.

Software definable digital input/output pins.

Receive analog negative input.

Receive analog positive input.

Transmit analog negative output 1

Transmit analog negative output 2

Transmit analog positive output 1

Transmit analog positive output 2

Serial interface clock. With master mode and SCLK continuous selected,

Freq = 256*Fs ( =2.4576MHz for Fs=9.6kHz). For slave mode, this pin

must be pulled down by a resistor (<4.7kΩ).

Serial data output (or input to the host).

Serial data input (or output from the host)

Frame synchronization. (Active Low)

Type of frame sync. 0 = late (mode0); 1 = early (mode1). Weak-pulled

high – default

Controls the SCLK behavior after FS. Open, weak-pulled high = SCLK

Continuous; tied low = 32 clocks per R/W cycle.

Delayed frame sync to support daisy chain mode with additional

73M1903C devices

RST

I

26

OSCIN

OSCOUT

GPIO(0-7)

RXAN

RXAP

TXAN1

TXAN2

TXAP1

TXAP2

SCLK

SDOUT

SDIN

FS

TYPE

SckMode

FSD

I

O

I/O

I

I

O

O

O

O

I/O

O

I

O

I

I

O

19

18

3, 4, 5, 6, 23 24,

30, 31

14

15

10

11

12

13

8

32

29

7

27

28

21

Table 1: 32 QFN Pin Description

Page: 4 of 46

©

2005-2008 TERIDIAN Semiconductor Corporation

Rev 4.3