DS_1x66B_001
73M1866B/73M1966B Data Sheet
CS
SCLK
SDI
CONTROL
ADDRESS
DATA [7:0]
DATA [7:0]
HI-Z
SDO
Figure 17: SPI Read Transaction – 8-bit Mode
In 16-bit mode, the first frame of 16 bits contains both the control and address bytes, and the second
frame contains the data bytes. Note that the second part of the second frame is irrelevant. Figure 18 and
Figure 19 show the write and read transactions in 16-bit mode.
CS
SCLK
CONTROL
ADDRESS
DATA[7:0]
XXXXXXXX
SDI
HI-Z
SDO
Figure 18: SPI Write Transaction – 16-bit Mode
CS
SCLK
SDI
CONTROL
ADDRESS
HI-Z
XXXXXXXX
DATA[15:8]
XXXXXXXX
DATA[7:0]
SDO
Figure 19: SPI Read Transaction – 16-bit Mode
The transaction diagrams show the case where SCLK is only active during the transaction frames. The
same transaction remains valid even if SCLK runs continuously, regardless of frame boundaries.
The SPI state machine resets when the host sends a frame containing a number of SCLK periods
different from a multiple of eight:
Rev. 1.6
35
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
