73M1822/73M1922 Data Sheet
DS_1x22_017
6.3 Power Management
The 73M1x22 supports three modes of power control for the device.
Normal mode
Sleep mode
The 73M1x22 operates normally.
The device PLL is turned off and the internal clock is driven by Xtal.
SCK=1/8 Xtal. Control and status registers maintain their content.
Power Down
The device is shut down altogether. In this mode the MAFE is
disabled together with the Xtal oscillator. To restart the normal
operations, RESET or power on reset is required.
Function
Mnemonic Location
Register
Type Description
SLEEP
PWDN
IDL2
0x0F[5]
0x0F[6]
0x19[4]
0x0F[7]
W
W
W
W
Sleep Mode
0 = Disable Sleep Mode.
1 = Enable Sleep Mode. (Default)
Power Down Mode
0 = Disable Power Down Mode. (Default)
1 = Enable Power Down Mode.
Ring Detect Functions
0 = Disable ring detect monitoring A/D function. (Default)
1 = Enable ring detect monitoring A/D function.
ENFEH
Enable Front End Host
1 = Enable Front End of the 73M1902 Host-Side Device.
0 = Disable Front End of the 73M1902 Host-Side Device. (Default)
6.4 Device Clock Management
Function
Mnemonic
Register
Location
Type Description
FRCVCO
0x0E[7]
W
Force VCO
0 = The system clock is driven from the Xtal oscillator. (Default)
1 = The system clock is derived from locked PLL. This is set to 0
upon reset, Sleep or Power Down mode enabled.
PWDNPLL
XIB
0x0E[6]
R
PLL Powered Down
0 = PLL is not powered down. (Default)
1 = PLL is powered down.
0x0F[3:2]
W
Crystal Oscillator Bias Current Control
00 = Crystal oscillator bias current at 120 μA
01 = Crystal oscillator bias current at 180 μA
10 = Crystal oscillator bias current at 270 μA
11 = Crystal oscillator bias current at 450 μA (Default)
If OSCIN is used as a clock input, XIB = 00 setting should be used to
save power (=167 μA at 27.648 MHz).
38
Rev. 1.6
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
