DS_1x22_017
73M1822/73M1922 Data Sheet
5 Control and Status Registers
Table 30 shows the register map of addressable registers for the 73M1822 and 73M1922. The shaded
cells in the register map indicate read only and cannot be modified. Reserved bits should be left in their
default state. Accessing unspecified registers should be avoided. Each register and bit is described in
detail in the following sections.
For registers 0x12 through 0x1F, which are located in the Line-Side Device, there is a minimum time
between consecutive write transactions of 300 µs.
Table 30: Control and Status Register Map
Address
(hex)
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
00h/9Ch
00h
F0h
F7h
0Bh
00h
00h
DAh
EFh
31h
2Ah
06h
42h
00h
2Ch
00h
00h
00h
00h
00h
01h
00h
01h
00h
00h
00h
00h
90h
00h
00h
DSYEN
TMEN
NSLAVE2 NSLAVE1 NSLAVE0
MSIDEN
Reserved
RGMON
MSID
ENLPW
DET
SCK32
SPOS
SYNL
Reserved
HC
Reserved
GPIO6
DIR6
Reserved
GPIO5
DIR5
Reserved
GPIO4
DIR4
GPIO7
DIR7
RGDT
REVHSD3 REVHSD2 REVHSD1 REVHSD0
ENAPOL ENDET ENSYNL ENRGDT
Reserved Reserved Reserved Reserved
ENGPIO7
POL7
ENGPIO6 ENGPIO5
ENGPIO4
POL4
POL6
Reserved
PSEQ6
PRST1
ICHP2
POL5
Reserved
PSEQ5
PRST0
Reserved
PSEQ7
PRST2
ICHP3
Reserved
PSEQ4
PDVSR4
ICHP0
DTST3
PSEQ3
DTST2
PSEQ2
DTST1
PSEQ1
DTST0
PSEQ0
PDVSR0
KVCOH0
NDVSR0
NSEQ0
NRST0
PDVSR3 PDVSR2 PDVSR1
Reserved KVCOH2 KVCOH1
NDVSR3 NDVSR2 NDVSR1
ICHP1
Reserved
NSEQ7
LOKDET
FRCVCO
ENFEH
Reserved
OFH
NDVSR6
NSEQ6
SLHS
NDVSR5
NSEQ5
Reserved
NDVSR4
NSEQ4
Reserved
Reserved
Reserved
CMVSEL
ENSHL
ACCEN
Reserved
CIDM
NSEQ3
NSEQ2
NRST2
NSEQ1
NRST1
RGTH1
CHNGFS
PWDNPLL Reserved
Reserved Reserved
XIB1 XIB0
CMTXG1 CMTXG0 CMRXG1 CMRXG0
RGTH0
PWDN
Reserved
ENDC
DCIV0
DAA1
SLEEP
Reserved
ENAC
Reserved Reserved
ENLVD
PLDM
ENFEL
OVDTH
RLPNH
ENUVD
FSCTR2
ENDT
IDISPD1
RXG1
ENNOM
IDISPD0
RXG0
DCIV1
ILM
TXBST
Reserved
TXEN
DAA0
RXBST
THEN
DISNTR
RXEN
Reserved
TEST2
MATCH
RNG6
Reserved
RLPNEN
Reserved
TEST1
Reserved
RNG5
ENOVD
FSCTR1
ENOID
ATEN
FSCTR3
ACZ0
FSCTR0
APWS
TEST3
POLL
ACZ1
Reserved Reserved Reserved
TEST0
IDL2
Reserved Reserved Reserved Reserved
INDX3
RNG3
LV3
INDX2
RNG2
LV2
INDX1
RNG1
LV1
INDX0
RNG0
RNG7
RNG4
LV7
LV6
LV5
LV4
Reserved
Reserved
LC6
LC5
LC4
LC3
LC2
LC1
LC0
REVLSD3
ILMON
POLVAL7
REVLSD2 REVLSD1 REVLSD0
UVDET OVDET OIDET
POLVAL6 POLVAL5 POLVAL4
Reserved Reserved Reserved Reserved
SLLS Reserved Reserved Reserved
POLVAL3 POLVAL2 POLVAL1 POLVAL0
Rev. 1.6
33
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