DS_1x22_001
73M1822/73M1922 Data Sheet
3.3 Serial Interface Timing Specification
The 73M1x22 has a synchronous serial interface, called the MAFE interface, to transfer data to and from a
host. Table 10 provides the timing specification for the MAFE interface.
Table 10: Serial Data Port Timing at 8 kHz Sample Rate
Parameter
Min
–
Nom
Max Unit
SCLK period (Tsclk)
1/1.536 MHz
–
ns
ns
ns
ns
ns
ns
ns
ns
SCLK to FS delay (td1) – mode1
SCLK to FS delay (td2) – mode1
SCLK to SDOUT delay (td3) with 10 pf load
Setup time SDIN to SCLK (tsu)
Hold time SDIN to SCLK (th)
SCLK to FS delay (td4) – mode 0
SCLK to FS delay (td5) – mode 0
–
–
–
–
–
–
–
–
20
20
20
–
–
–
15
10
–
–
20
20
–
SCLK
FS
(mode1)
SDOut
SDIN
FS
(mode0)
Figure 7: MAFE Timing Diagram
3.4 Analog Specifications
This section provides the electrical characterizations of the 73M1x22 analog circuitry.
3.4.1 DC Specifications
VBG is to be connected to an external bypass capacitor with a minimum value of 0.1 μF. This pin is not
intended for any other external use.
Table 11: Reference Voltage Specifications
Parameter
VBG
Test Condition
Min
0.9
–
Nom
1.19
-86
–
Max
1.4
-80
–
Units
V
VDD=3.0 V – 3.6 V
300 Hz – 3.3 kHz
VBG Noise
dBm600
dB
VBG PSRR 300 Hz – 30 kHz
40
Rev. 1.6
19
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