73M1822/73M1922 Data Sheet
DS_1x22_001
Pin
Pin Name
Number
Type
Description
Controls the SCLK behavior after FS. Weak-pulled high –
default = continuous SCLK
14
SCKM
I
15
16
17
18
19
20
21
VNM/VNT
GND
I
Negative barrier interface/transformer supply
Master/slave control, reset at a transition
Pulse transformer primary minus
M/S
PRM
PRP
I/O
I/O
I
Pulse transformer primary plus
Factory test mode – leave open
RST
VPD
LEV
PWR
O
Positive digital supply, positive transformer supply
Test output (CMOS level)
Ring detection indicator or other Interrupts.
Open drain
22
O
INT/RGDT
Serial interface clock. With continuous SCLK selected,
Frequency = 256∗Fs (=1.8432MHz for Fs=7.2kHz, 2.048MHz
for Fs=8kHz)
23
SCLK
O
24
25
26
27
28
29
30
31
32
VND
GND
I
Negative digital ground
SDIN
SDOUT
VPD
Serial data input (or output from the controller to 73M1902)
Serial data output (or input to the controller from 73M1902)
Positive digital supply, positive transformer supply
FS delayed
O
PWR
O
FSD
O
Frame synchronization
FS
VND
GPIO7
GPIO6
GND
I/O
I/O
Negative digital ground
Configurable digital input/output pins
Configurable digital input/output pins
12
Rev. 1.6
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
