73K324BL-IHR/F 参数 Datasheet PDF下载

73K324BL

CCITT V.22bis,V.23,V.22,V.21, Bell 212A

Single-Chip Modem w/ Integrated Hybrid

DATA SHEET

REGISTER DESCRIPTIONS

Eight 8-bit internal registers are accessible for

control and status monitoring. The registers are

accessed in read or write operations by addressing

the AD0, AD1 and AD2 lines in serial mode, or in

parallel mode. The address lines and

CS

are latched

by ALE in the parallel mode. Register CR0 controls

the method by which data is transferred over the

phone line. CR1 controls the interface between the

microprocessor and the 73K324BL internal state.

DR is a detect register which provides an indication

REGISTER BIT SUMMARY

ADDRESS

REGISTER

CONTROL

REGISTER

0

CONTROL

REGISTER

1

DETECT

REGISTER

AD-A0

D7

MODULATION

OPTION

D6

MODULATION

TYPE

1

TRANSMIT

PATTERN

0

PATTERN

S1 DET

D5

MODULATION

TYPE

0

ENABLE

DETECT

INTERRUPT

RECEIVE

DATA

D4

TRANSMIT

MODE

2

BYPASS

SCRAMBLER

D3

TRANSMIT

MODE

1

D2

TRANSMIT

MODE

0

D1

TRANSMIT

ENABLE

D0

ANSWER/

ORIGINATE

of monitored modem status conditions. TR, the tone

control register, controls the DTMF generator,

answer and guard tones and RXD output gate used

in the modem initial connect sequence. CR2 is the

primary DSP control interface and CR3 controls

transmit attenuation and receive gain adjustments.

All registers are read/write except for DR and ID,

which are read only. Register control and status bits

are identified below:

CR0

000

CR1

001

TRANSMIT

PATTERN

1

RECEIVE

LEVEL

CLK

CONTROL

RESET

TEST MODE

1

TEST MODE

0

DR

010

UNSCR.

MARK

DETECT

TRANSMIT

DTMF

CARRIER

DETECT

SPECIAL

TONE

DETECT

DTMF2/

4W/FDX

CALL

PROGRESS

DETECT

DTMF1/

EXTENDED

OVERSPEED

TRAIN

INHIBIT

SIGNAL

QUALITY

TONE

CONTROL

REGISTER

CONTROL

REGISTER

2

CONTROL

REGISTER

3

SPECIAL

REGISTER

ID

REGISTER

TR

011

RXD

OUTPUT

CONTROL

TRANSMIT

GUARD

TONE

SPECIAL

REGISTER

ACCESS

TRISTATE

TX/RXCLK

TRANSMIT

ANSWER

TONE

CALL

INITIALIZE

DTMF 3

DTMF0/

GUARD/

ANSWER

EQUALIZER

ENABLE

CR2

100

0

TRANSMIT

S1

16 WAY

RESET

DSP

TXDALT

CR3

101

OH

RECEIVE

GAIN

BOOST

TRANSMIT

ATTEN.

3

TXD

SOURCE

TRANSMIT

ATTEN.

2

SQ

SELECT 1

TRANSMIT

ATTEN.

1

SQ

SELECT 0

TRANSMIT

ATTEN.

0

SR

101

0

TX BAUD

CLOCK

RX UNSCR.

DATA

0

0

ID

110

ID

ID

ID

ID

X

X

X

1

NOTE:

When a register containing reserved control bit is written into, the reserved bits must be programmed as

0’s.

X = Undefined, mask in software

Page: 9 of 34

©

2005, 2008 TERIDIAN Semiconductor Corporation

Rev 6.1