73K224L
V.22bis, V.22, V.21, Bell 212A, 103
Single-Chip Modem
DATA SHEET
REGISTER DESCRIPTIONS
Eight 8-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the A0, A1 and
A2 address lines in serial mode, or the AD0, AD1 and
AD2 lines in parallel mode. The address lines are
latched by ALE. Register CR0 controls the method by
which data is transferred over the phone line. CR1
controls the interface between the microprocessor and
the 73K224L internal state. DR is a detect register
REGISTER BIT SUMMARY
ADDRESS
DATA BIT NUMBER
which provides an indication of monitored modem
status conditions. TR, the tone control register,
controls the DTMF generator, answer and guard
tones and RXD output gate used in the modem
initial connect sequence. CR2 is the primary DSP
control interface and CR3 controls transmit
attenuation and receive gain adjustments. All
registers are read/write except for DR and ID,
which are read only. Register control and status
bits are identified below:
REGISTER
AD - A0
D7
D6
D5
D4
D3
D2
D1
D0
CONTROL
REGISTER
0
CONTROL
REGISTER
1
CR0
000
MODULATION
OPTION
MODULATION
TYPE
1
TRANSMIT
PATTERN
0
MODULATON
TYPE
0
ENABLE
DETECT
INTERRUPT
TRANSMIT
MODE
2
TRANSMIT
MODE
1
TRANSMIT
MODE
0
TRANSMIT
ENABLE
ANSWER/
ORIGINATE
CR1
001
TRANSMIT
PATTERN
1
BYPASS
SCRAMBLER
CLK
CONTROL
RESET
TEST
MODE
1
CALL
PROGRESS
DETECT
DTMF1/
EXTENDED
OVERSPEED
TEST
MODE
0
DETECT
REGISTER
DR
010
RECEIVE
LEVEL
PATTERN
S1 DET
RECEIVE
DATA
UNSCR.
MARK
DETECT
CARRIER
DETECT
SPECIAL
TONE
DETECT
SIGNAL
QUALITY
TONE
CONTROL
REGISTER
CONTROL
REGISTER
2
CONTROL
REGISTER
3
TR
011
RXD
OUTPUT
CONTOL
TRANSMIT
GUARD
TONE
SPECIAL
REGISTER
ACCESS
TRANSMIT
ANSWER
TONE
TRANSMIT
DTMF
DTMF3
DTMF2/
4W/FDX
DTMF0/
GUARD/
ANSWER
CR2
100
0
CALL
INITIALIZE
TRANSMIT
S1
16 WAY
RESET
DSP
TRAIN
INHIBIT
EQUALIZER
ENABLE
CR3
101
TXDALT
TRISTATE
TX/RXCLK
0
RECEIVE
GAIN
BOOST
TRANSMIT
ATTEN.
3
TRANSMIT
ATTEN.
2
TRANSMIT
ATTEN.
1
TRANSMIT
ATTEN.
0
SPECIAL
REGISTER
SR
101
0
TX BAUD
CLOCK
RX UNSCR.
DATA
0
TXD
SOURCE
SQ
SELECT 1
SQ
SELECT 0
0
ID
REGISTER
ID
110
ID
ID
ID
ID
X
X
X
1
NOTE: When a register containing reserved control
bits is written into, the reserved bits must be
programmed as 0's.
X = Undefined, mask in software
Page: 6 of 31
©
2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
