73K224L
V.22bis, V.22, V.21, Bell 212A, 103
Single-Chip Modem
DATA SHEET
CONTROL REGISTER 2 (continued)
D7
D6
D5
D4
D3
D2
D1
D0
CR2
100
0
SPEC REG CALL INIT
ACCESS
TRANSMIT
S1
16WAY
RESET
DSP
TRAIN
INHIBIT
EQUALIZER
ENABLE
BIT NO.
NAME
CONDITION
DESCRIPTION
D4
Transmit S1
0
The transmitter when placed in alternating mark/space
mode transmits 0101...... scrambled or not dependent on
the bypass scrambler bit.
1
When this bit is 1 and only when the transmitter is placed in
alternating mark/space mode by CR1 bits D7, D6, and in
DPSK or QAM, an unscrambled repetitive double dibit
pattern of 00 and 11 at 1200 bit/s (S1) is sent.
D5
Call Init
0
1
DEMOD mode: The DSP is setup to do demodulation and
pattern detection based on the various mode bits. Both
answer tones are detected in demod mode concurrently (wide
band detection); TR-D0 is ignored.
CALL INIT mode: The DSP decodes unscrambled mark,
answer tone and call progress tones.
D6
D7
Special
Register
Access
0
1
Normal CR3 access.
Setting this bit and addressing CR3 allows access to the
SPECIAL REGISTER. See the SPECIAL REGISTER for
details.
Not used at this time
0
Only write zero to this bit.
CONTROL REGISTER 3
D7
D6
D5
D4
D3
D2
D1
D0
CR3
101
TXDALT
TRISTATE
TX/RXCLK
0
RECEIVE
BOOST
TRANSMIT TRANSMIT
TRANSMIT
ATTEN. 1
TRANSMIT
ATTEN. 0
ATTEN. 3
ATTEN. 2
ENABLE
BIT NO.
NAME
CONDITION
DESCRIPTION
D3, D2,
D1,D0
Transmit
Attenuator
D3 D2 D1 D0 Sets the attenuation level of the transmitted signal in 1dB
steps. The default (D3-D0=0100) is for a transmit level of –
10 dBm0 on the line with the recommended hybrid transmit
gain. The total range is 16 dB.
0
1
0
1
0
1
0
1
D4
Receive Gain
Boost
0
1
18 dB receive front end boost is not used.
Boost is in the path. This boost does not change reference
levels. It is used to extend dynamic range by compensating
for internally generated noise when receiving weak signals.
The receive level detect signal and knowledge of the hybrid
and transmit attenuator setting will determine when boost
should be enabled.
Not used at this time
D5
D6
0
0
1
Only write zero to this bit.
TRISTATE
TXCLK/RXCLK
TXCLK and RXCLK are driven.
TXCLK and RXCLK are tri-stated.
Alternate TX data source. See Special Register.
Spec. Reg. Bit D3=1
D7
TXDALT
Page: 15 of 31
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
