73K224BL
V.22bis, V.22, V.21, Bell 212A, 103
Single-Chip Modem w/ Integrated Hybrid
DATA SHEET
DYNAMIC CHARACTERISTICS AND TIMING (continued)
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
TIMING
*
(Refer to Timing Diagrams)
TAL
CS/Address setup before ALE Low
CS
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TLA
CS
AD0-AD7
Address hold after ALE Low
ALE Low to RD/WR Low
RD/WR Control to ALE High
Data out from RD Low
ALE width
10
10
0
TLC
TCL
TRD
TLL
0
70
50
15
TRDF
TRW
TWW
TDW
TWD
TCKD
Data float after RD High
RD width
50
150
15
WR width
Data setup before WR High
Data hold after WR High
Data out after EXCLK Low
WR after EXCLK Low
Data setup before EXCLK Low
Address setup before control**
Address hold after control**
Data Hold after EXCLK
12
200
TCKW (serial mode)
TDCK (serial mode)
TAC (serial mode)
TCA (serial mode)
TWH (serial mode)
150
150
50
50
50
* All timing parameters are targets and not guaranteed.
** Control for setup is the falling edge of RD or WR. Control for hold is the falling edge of RD or the rising edge
of WR.
NOTE: Asserting ALE, CS, and RD or WR concurrently can cause unintentional register accesses. When
using non-8031 compatible processors, care must be taken to prevent this from occurring when
designing the interface logic.
Page: 26 of 33
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
