73K222AL
V.22, V.21, Bell 212A, 103
Single-Chip Modem
DATA SHEET
REGISTER DESCRIPTIONS
Four 8-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the A0, A1
and A2 address lines in serial mode, or the AD0,
AD1 and AD2 lines in parallel mode. In parallel
mode the address lines are latched by ALE. Register
CR0 controls the method by which data is
transferred over the phone line. CR1 controls the
interface between the microprocessor and the
REGISTER BIT SUMMARY
73K222AL internal state. DR is a detect register
which provides an indication of monitored
modem status conditions. TR, the tone control
register, controls the DTMF generator, answer
and guard tones and RXD output gate used in
the modem initial connect sequence. All
registers are read/write except for DR, which is
read only. Register control and status bits are
identified below:
ADDRESS
REGISTER
CONTROL
REGISTER
0
CONTROL
REGISTER
1
DETECT
REGISTER
AD2 - AD0
000
D7
MODULATION
OPTION
TRANSMIT
PATTERN
1
X
D6
0
D5
TRANSMIT
MODE
3
ENABLE
DETECT
INTERRUPT
RECEIVE
DATA
DATA BIT NUMBER
D4
TRANSMIT
MODE
2
BYPASS
SCRAMBLER
D3
TRANSMIT
MODE
1
CLK
CONTROL
D2
TRANSMIT
MODE
0
D1
TRANSMIT
ENABLE
D0
ANSWER/
ORIGINATE
CR0
CR1
001
TRANSMIT
PATTERN
0
X
RESET
TEST
MODE
1
CALL
PROGRESS
TEST
MODE
0
LONG
LOOP
DR
010
UNSCR.
MARKS
CARRIER
DETECT
ANSWER
TONE
TONE
CONTROL
REGISTER
CONTROL
REGISTER
2
CONTROL
REGISTER
3
ID
REGISTER
TR
011
RXD
OUTPUT
CONTROL
X
TRANSMIT
GUARD
TONE
X
TRANSMIT
ANSWER
TONE
X
TRANSMIT
DTMF
DTMF3
DTMF2
DTMF1/
OVERSPEED
DTMF0/
GUARD/
ANS TONE
X
CR2
100
THESE REGISTER LOCATIONS ARE RESERVED FOR
CR3
101
X
X
X
USE WITH OTHER K-SERIES FAMILY MEMBERS
X
ID
110
ID
ID
ID
ID
X
X
X
X
NOTE: When a register containing reserved control
bits is written into, the reserved bits must be
programmed as 0's.
X = Undefined, mask in software
Page: 7 of 27
©
2007 TERIDIAN Semiconductor Corporation
Rev 6.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
