Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
4
Firmware Interface
4.1
I/O RAM and SFR Map – Functional Order
In Table 54, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits have no memory storage, writing them has no
effect, and reading them always returns zero. Reserved bits may be in use and should not be changed from the values given in parentheses.
Writing values other than those shown in parenthesis to reserved bits may have undesirable side effects and must be avoided.
Non-volatile bits are shaded in dark gray. Non-volatile bits are backed-up during power failures if the system includes a battery connected to the
VBAT pin.
This table lists only the SFR registers that are not generic 8051 SFR registers. Bits marked with † apply to the 71M6531D/F only, bits marked with
‡ apply to the 71M6532D/F only and should be 0 for the other device.
Table 54: I/O RAM Map in Functional Order
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Configuration:
CE0
2000
EQU[2:0]
CE_E
CE10MHZ
U
CE1
CE2
2001
2002
2003
2004
2005
2006
2007
209D
20A7
20A8
20A9
20AA
20AB
20AC
20AD
PRE_SAMPS[1:0]
SUM_CYCLES[5:0]
RTM_E WD_OVF
U
CHOP_E[1:0]
EX_RTC
EX_XFR
COMP_STAT
COMP0
CONFIG0
CONFIG1
VERSION
CONFIG2
CE3
CE4
CE5
WAKE
TMUX
U
VREF_CAL
U
PLL_OK
PLS_INV
U
U
U
U
U
U
U
CKOUT_E
M26MHZ
VREF_DIS
ADC_E
MPU_DIV[2:0]
ECK_DIS
MUX_ALT
U
M40MHZ
VERSION[7:0]
EX_FWCOL
OPT_TXE[1:0]
EX_PLL
FIR_LEN[1:0]
OPT_FDC[1:0]
U
MUX_DIV[3:0]
BOOT_SIZE[7:0]
CE_LCTN[7:0]
WAKE_RES
WAKE_ARM
SLEEP
LCD_ONLY
U
WAKE_PRD[2:0]
U
TMUX[4:0]
LCD_DAC[2:0]
U
U
ANACTRL
CONFIG3
CONFIG4
R (0000)
SEL_IBN‡
CHOP_I_EN‡
CHOP_IA‡
R (0)
U
U
CHOP_IB‡
SEL_IAN‡
R (0)
R (0)
R (0)
Interrupts and WD Timer:
INTBITS
IFLAGS
SFR F8
WD_RST
INT6
INT5
IE_WAKE
INT4
IE_PB
INT3
INT2
INT1
IE_RTC
INT0
IE_XFER
SFR E8 IE_PLLFALL IE_PLLRISE
IE_FWCOL1 IE_FWCOL0
Flash Memory:
ERASE
FLSHCTL
SFR 94
SFR B2
FLSH_ERASE[7:0]
WRPROT_BT WRPROT_CE
PREBOOT
SECURE
U
FLSH_MEEN
FLBANK[2:0]
U
FLSH_PWE
FL_BANK SFR B6
PGADR
SFR B7
72
U
FLSH_PGADR[5:0]
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