Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Appendix B: Revision History
Revision
Date
Description
1.3
June 9, 2010
1) Throughout document: Added bit ranges to all register fields where
missing (e.g. MPU_DIV[2:0]).
2) Figure 1, Figure 2: corrected name for PSDI and PSDO signals.
3) 1.4 80515 MPU Core
Added SFR register addresses where needed.
(Page 19) Table 6: Change approximate frequencies to exact
frequencies.
(Page 19) Changed providing Library to providing demonstration
source code.
(Page 20) Added note about MUX_DIV=0 disables ADC output.
(Page 21) See restrictions on INTBITS register.
(Page 22) Added P1-P3 to Table 10.
(Page 23) Updated Data Pointer description.
(Page 24) Table 14: Updated description for FWCOL0, FWCOL1.
(Page 26) 1.4.6 UARTs: Clarified SOBUF, S1BUF as Tx and Rx
buffers.
(Page 27) Added caution on proper way to clear flag bits.
(Page 30) 1.4.9 Interrupts: Clarified External vs Internal interrupts.
(Page 31) Table 25: Added Interrupt sources for Ext. Interrupts 2-6.
4) 1.5.2 Internal Clocks
(Page 36) Table 37: Changed frequencies to exact frequencies.
(Page 38) Added caution concerning frequency relationship to
specific CE code.
5) 1.5.3 Real-Time Clock (RTC): (Page 39) Added description for
observing RTC timing on TMUXOUT pin, corrected values for
RTCA_ADJ, and achievable frequency step.
6) 1.5.9 Digital IO – Common Characteristics for 71M6531D/F and
71M6532D/F (Page 45):
Added caution about not sourcing current in or out of DIO pins.
Updated Figure 10 : Connecting an External Load to DIO Pins.
7) 1.5.13 Battery Monitor (Page 46): Corrected RAM address for
ADC data.
8) 1.5.15 SPI Slave Port (page 49): Clarified description of I/O RAM
access via the SPI interface. Added Table 50.
9) 2.3 Battery Modes (page 56, 57): Added details on software pre-
cautions for switching between modes and factory programming of
the first 6 flash addresses.
10)
3.1 Connection of Sensors (page 63): Added note concerning
analog input pins requiring sensors with low source impedance.
11) 3.15 MPU Firmware (page 70): Modified to indicate demonstration
source code provided.
12) 3.16 Crystal Oscillator (page 70): Updated caution concerning
rejecting electromagnetic interference.
13) Table 54: I/O RAM Map in Functional Order (page 72): Updated
Unused and NVRAM locations.
14) 4.3.4 Environment: Added comment concerning importance of
parameter dependence on CE code environment.
15) 4.3.6 CE Status and Control (page 89):
Updated description of F0 in Table 57.
Updated descriptions in Table 58 (page 91).
16) 4.3.7 CE Transfer Variables: Updated description of
VBAT_SUM_X in Table 63 (page 93).
17) Corrected values for EXT_PULSE in description of internal pulse
118
© 2005-2010 TERIDIAN Semiconductor Corporation
v1.3
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