FDS_6533_6534_004
71M6533/71M6534 Data Sheet
1.2.14 CE Functional Overview
The ADC processes one sample per channel per multiplexer cycle. Figure 5 shows the timing of the
samples taken during one multiplexer cycle (phases A, B, and C being processed). During an ALT mul-
tiplexer sequence, missing samples are filled in by the CE.
The number of samples processed during one accumulation cycle is controlled by the I/O RAM registers
PRE_SAMPS (0x2001[7:6]) and SUM_CYCLES (0x2001[5:0]). The integration time for each energy output is:
PRE_SAMPS * SUM_CYCLES / 2520.6, where 2520.6 is the sample rate in Hz
For example, PRE_SAMPS = 42 and SUM_CYCLES = 50 will establish 2100 samples per accumulation
cycle. PRE_SAMPS = 100 and SUM_CYCLES = 21 will result in the exact same accumulation cycle of 2100
samples or 833 ms. After an accumulation cycle is completed, the XFER_BUSY interrupt signals to the
MPU that accumulated data are available.
1/2520.6Hz = 397µs
IB
2/32768Hz =
B
61.04µs
VB
A
IC
VC
IA
VA
C
13/32768Hz = 397µs
per mux cycle
Figure 5: Samples from Multiplexer Cycle
The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each
multiplexer cycle, status information, such as sag data and the digitized input signal, is available to the MPU.
833ms
20ms
XFER_BUSY
Interrupt to MPU
Figure 6: Accumulation Interval
Figure 6 shows the accumulation interval resulting from PRE_SAMPS = 42 and SUM_CYCLES = 50, con-
sisting of 2100 samples of 397µs each, followed by the XFER_BUSY interrupt. The sampling in this ex-
ample is applied to a 50 Hz signal.
v1.1
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