FDS_6533_6534_004
71M6533/71M6534 Data Sheet
Name
DIO6
Address
200E
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Not Used
DIO_R11[2:0]
Not Used
Not Used
DIO_PX
DIO_R10[2:0]
Not Used
200F
Reserved (00)
Not Used
DIO_PY
Not Used
UMUX_E*
UMUX_SEL*
DIO7/ P0 SFR 80
DIO8
SFR A2
DIO_0[7:0](Port 0)
DIO_DIR0[7:1]
Not Used
Not Used
DIO9 / P1 SFR 90
(Port 1)
DIO_1[7:5]
DIO_1[3:0]
DIO_DIR1[3:0]
DIO_1[4]*
DIO10
SFR 91
DIO_DIR1[7:5]
Not Used
DIO_DIR[4]*
DIO11/ P2 SFR A0
(Port 2)
DIO_2[7]
Not Used
DIO_2[6]*
Not Used
DIO_2[5:0]
DIO_DIR2[5:0]
DIO3[3] DIO3[2]
DIO12
P3
SFR A1 DIO_DIR2[7]
SFR B0 Not Used
DIO_DIR2[6]*
DIO3[6]
DIO3[5]
Not Used
DIO3[1]
DIO3[0]
DIO3[4]*
Interrupts and WD Timer:
INTBITS
IFLAGS
Flash:
ERASE
SFR F8
WD_RST
INT6
INT5
INT4
INT3
INT2
INT1
INT0
SFR E8 IE_PLLFALL IE_PLLRISE
IE_WAKE
IE_PB
IE_FWCOL1
IE_FWCOL0
IE_RTC
IE_XFER
SFR 94
FLSH_ERASE[7:0]
FLSHCTL SFR B2
FL_BANK SFR B6
PREBOOT
SECURE
WRPROT_BT WRPROT_CE
Not Used
Not Used
Not Used
Not Used
FLSH_MEEN
FLSH_PWE
Not Used
Not Used
Not Used
Not Used
FL_BANK[1:0]
FL_BANK[2:0]*
PGADR
SFR B7
FLSH_PGADR[5:0]
Not Used
Not Used
Real Time Clock:
RTCCTRL 2010
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
RST_SUBSEC
RTCA_ADJ 2011
SUBSEC1 2014
RTCA_ADJ[6:0]
SUBSEC[7:0]
RTC0
RTC1
RTC2
RTC3
RTC4
2015
2016
2017
2018
2019
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
RTC_SEC[5:0]
RTC_MIN[5:0]
RTC_HR[4:0]
Not Used
Not Used
Not Used
Not Used
Not Used
RTC_DAY[2:0]
RTC_DATE[2:0]
v1.1
© 2007-2009 TERIDIAN Semiconductor Corporation
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TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
