FDS_6533_6534_004
71M6533/71M6534 Data Sheet
2.3 Battery Modes
Shortly after system power (V3P3SYS) is applied, the part will be in MISSION mode. MISSION mode
means that the part is operating with system power and that the internal PLL is stable. This mode is the
normal operation mode where the part is capable of measuring energy.
When system power is not available (i.e. when V1<VBIAS), the 71M6533 and 71M6534 will be in one of
three battery modes: BROWNOUT, LCD, or SLEEP mode. Figure 20 shows a state diagram of the vari-
ous operation modes, with the possible transitions between modes. For information on the timing of
mode transitions refer to Figure 24 through Figure 26.
When V1 falls below VBIAS or the part wakes up under battery power, the part will automatically enter
BROWNOUT mode (see Section 2.5 Wake Up Behavior). From BROWNOUT mode, the part may enter
either LCD mode or SLEEP mode, as controlled by the MPU via the I/O RAM bits LCD_ONLY and SLEEP.
RESET
MISSION
V3P3SYS
falls
V1 > VBIAS
V1 <= VBIAS
IE_PLLRISE
IE_PLLFALL
V3P3SYS
rises
V3P3SYS
rises
LCD_ONLY
BROWNOUT
V3P3SYS
rises
RESET &
VBAT_OK
IE_PB
IE_WAKE
PB
SLEEP or
VBAT_OK
timer
LCD
timer
PB
VBAT_OK
VBAT_OK
RESET &
VBAT_OK
SLEEP
Figure 20: Operation Modes State Diagram
The transition from MISSION mode to BROWNOUT mode is signaled by the IE_PLLFALL interrupt flag
(SFR 0xE8[7]). The transition in the other direction is signaled by the IE_PLLRISE interrupt flag (SFR
0xE8[6]), when the PLL becomes stable.
Transitions from both LCD and SLEEP mode are initiated by wake-up timer timeout conditions or push-
button events. When the PB pin is pulled high (pushbutton is pressed), the IE_PB interrupt flag (SFR
0xE8[4]) is set, and when the wake-up timer times out, the IE_WAKE interrupt flag (SFR 0xE8[5]) is set.
In the absence of system power, if the voltage margin for the LDO regulator providing 2.5 V to the internal
circuitry becomes too low to be safe, the part automatically enters sleep mode (BAT_OK false). The battery
voltage must stay above 3 V to ensure that BAT_OK remains true. Under this condition, the 71M6533 and
71M6534 stays in SLEEP mode, even if the voltage margin for the LDO improves (BAT_OK true).
Table 45 shows the circuit functions available in each operating mode.
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