71M6533/71M6534 Data Sheet
FDS_6533_6534_004
2.2 System Timing Summary
Figure 18 summarizes the timing relationships between the input MUX states, the CE_BUSY signal and
the two serial output streams. In this example, MUX_DIV=6 and FIR_LEN=2 (384). The duration of each
MUX frame is (M40MHZ/M26MHZ = 00, 10, or 11 assumed):
•
•
•
1 + MUX_DIV * 1, if FIR_LEN = 0 (138 CE cycles), complete MUX frame = 7 CK32 cycles
1 + MUX_DIV * 2, if FIR_LEN = 1 (288 CE cycles) , complete MUX frame = 13 CK32 cycles
1 + MUX_DIV * 3, if FIR_LEN = 2 (384 CE cycles) , complete MUX frame = 19 CK32 cycles
An ADC conversion will always consume an integer number of CK32 clocks. Following this is a single
CK32 cycle where the bandgap voltage is allowed to recover from the change in CROSS. Figure 18
shows a typical MUX frame with if FIR_LEN = 1and MUX_DIV = 6.
ADC MUX Frame
MUX_DIV Conversions (MUX_DIV=6 is shown)
Settle
ADC TIMING
CK32
150
MUX_SYNC
ADC EXECUTION
ADC0
300
CK COUNT = CE_CYCLES + floor((CE_CYCLES + 2) / 4)
ADC1
ADC2
ADC3
ADC4
1500
MAX CK COUNT
ADC5
CE TIMING
CE_EXECUTION
0
600
900
1200
1800
CE_BUSY
XFER_BUSY
INITIATED BY A CE OPCODE AT END OF SUM INTERVAL
RTM TIMING
140
RTM
NOTES:
1. ALL DIMENSIONS ARE 4.9152 MHz CK COUNTS.
2. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES.
Figure 18: Timing Relationship between ADC MUX and Compute Engine
Each CE program pass begins when the ADC0 conversion (slot 0, as defined by SLOT0_SEL) begins.
Depending on the length of the CE program, it may continue running until the end of the last conversion.
CE opcodes are constructed to ensure that all CE code passes consume exactly the same number of
cycles. The result of each ADC conversion is inserted into the XRAM when the conversion is complete.
The CE code is written to tolerate sudden changes in ADC data. The exact CK count when each ADC
value is loaded into RAM is shown in Figure 18.
Figure 19 shows that the serial data stream, RTM, begins transmitting at the beginning of state S. RTM,
consisting of 140 CK cycles, will always finish before the next code pass starts.
CK32
MUX_SYNC
CKTEST
0
1
0
1
0
1
0
1
30
30 31
30 31
30 31
31
TMUXOUT/RTM
FLAG
FLAG
FLAG
FLAG
LSB
SIGN
LSB
LSB
LSB
RTM DATA 0 (32 bits)
RTM DATA 1 (32 bits)
RTM DATA 2 (32 bits)
RTM DATA 3 (32 bits)
SIGN
SIGN
SIGN
Figure 19: RTM Output Format
54
© 2007-2009 TERIDIAN Semiconductor Corporation
v1.1
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
