71M6533/71M6534 Data Sheet
3:0
CNT[3:0]
FDS_6533_6534_004
Specifies the number of clocks to be issued. Allowed values are 0
W
through 8. If RD=1, CNT bits of data will be read MSB first, and right
justified into the low order bits of EEDATA. If RD=0, CNT bits will be
sent MSB first to the EEPROM, shifted out of the MSB of EEDATA. If
CNT[3:0] is zero, SDATA will simply obey the HiZ bit.
The timing diagrams in Figure 10 through Figure 14 describe the 3-wire EEPROM interface behavior. All
commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that
is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 10 through Figure 14
are then sent via EECTRL and EEDATA.
When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM
will be driving SDATA, but will transition to HiZ (high impedance) when CS falls. The firmware should
then immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to
a low-Z state.
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- No HiZ
SCLK (output)
D7
D6
D5
D4
D3
D2
SDATA (output)
SDATA output Z
BUSY (bit)
(LoZ)
Figure 10: 3-wire Interface. Write Command, HiZ=0.
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- With HiZ
SCLK (output)
D7
D6
D5
D4
D3
D2
SDATA (output)
SDATA output Z
BUSY (bit)
(LoZ)
(HiZ)
Figure 11: 3-wire Interface. Write Command, HiZ=1
EECTRL Byte Written
INT5
CNT Cycles (8 shown)
READ
SCLK (output)
D7
D6
D5
D4
D3
D2
D1
D0
SDATA (input)
SDATA output Z
BUSY (bit)
(HiZ)
Figure 12: 3-wire Interface. Read Command.
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© 2007-2009 TERIDIAN Semiconductor Corporation
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