FDS_6533_6534_004
71M6533/71M6534 Data Sheet
1.3 80515 MPU Core
The 71M6533 and 71M6534 include an 80515 MPU (8-bit, 8051-compatible) that processes most instructions
in one clock cycle. Using a 10 MHz clock results in a processing throughput of 10 MIPS. The 80515 architec-
ture eliminates redundant bus states and implements parallel execution of fetch and execution phases. Nor-
mally, a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte instructions are performed
in a single machine cycle (MPU clock cycle). This leads to an 8x average performance improvement (in terms
of MIPS) over the Intel 8051 device running at the same clock frequency.
Table 6 shows the CKMPU frequency as a function of the allowed combinations of the MPU clock divider
MPU_DIV[2:0] and the MCK divider registers M40MHZ and M26MHZ. Actual processor clocking speed
can be adjusted to the total processing demand of the application (metering calculations, AMR manage-
ment, memory management, LCD driver management and I/O management) using the I/O RAM register
MPU_DIV[2:0] and the MCK divider registers M40MHZ and M26MHZ, as shown in Table 6.
Table 6: CKMPU Clock Frequencies
[M40MHZ, M26MHZ] Values
MPU_DIV [2:0]
[1,0]
10 MHz
[0,1]
[0,0]
000
001
010
011
100
101
110
111
6.6 MHz
5 MHz
5 MHz
3.3 MHz
2.5 MHz
1.25 MHz
625 kHz
2.5 MHz
1.25 MHz
625 kHz
1.65 MHz
825 kHz
412.5 kHz
206.25 kHz
103.13 kHz
103.13 kHz
312.5 kHz
156.25 kHz
78.13 kHz
78.13 kHz
312.5 kHz
156.25 kHz
156.25 kHz
Typical measurement and metering functions based on the results provided by the internal 32-bit com-
pute engine (CE) are available for the MPU as part of the Teridian standard library. A standard ANSI C
80515 application programming interface library is available to help reduce design cycle.
1.3.1 Memory Organization and Addressing
The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces. Memo-
ry organization in the 80515 is similar to that of the industry standard 8051. There are four memory
areas: Program memory (Flash, shared by MPU and CE), external RAM (Data RAM, shared by the CE
and MPU), Configuration RAM and internal data memory (Internal RAM). Table 7 shows the memory
map.
Program Memory
The 80515 can address up to 64 KB of program memory space from 0x0000 to 0xFFFF. Program memo-
ry is read when the MPU fetches instructions or performs a MOVC operation. Access to program memory
above 0x7FFF is controlled by the FL_BANK[2:0] register (SFR 0xB6).
After reset, the MPU starts program execution from program memory location 0x0000. The lower part of
the program memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte in-
tervals, starting from 0x0003.
MPU External Data Memory (XRAM)
Both internal and external memory is physically located on the 71M6533/71M6534 device. The external
memory referred to in this documentation is only external to the 80515 MPU core.
4 KB of RAM starting at address 0x0000 is shared by the CE and MPU. The CE normally uses the first
1 KB, leaving 3 KB for the MPU. Different versions of the CE code use varying amounts. Consult the
documentation for the specific code version being used for the exact limit.
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