Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Name
Location
Reset Wake
Dir
Description
L
LCD_DAC[2:0]
20AB[3:1]
0
R/W LCD contrast control DAC. Adjusts the LCD voltage in steps of 0.2 V from V3P3SYS
(mission mode) or VBAT (brownout/LCD modes).
LCD_DAC[2:0]
Resulting LCD Voltage
V3P3 or VBAT
000
001
010
011
100
101
110
111
V3P3 or VBAT – 0.2V
V3P3 or VBAT – 0.4V
V3P3 or VBAT – 0.6V
V3P3 or VBAT – 0.8V
V3P3 or VBAT – 1.0V
V3P3 or VBAT – 1.2V
V3P3 or VBAT – 1.4V
L
L
LCD_E
2021[5]
0
0
R/W Enables the LCD display. When disabled, VLC2, VLC1 and VLC0 are ground as are
the COM and SEG outputs.
LCD_MODE[2:0] 2021[4:2]
R/W The LCD bias mode. Use the LCD DAC in ANACTRL to reduce saturation. The num-
ber of states is the number of commons which are driven to multiplex the LCD.
LCD_MODE[2:0]
Function
Notes
000
001
010
011
100
4 states, ⅓ bias
3 states, ⅓ bias
2 states, ½ bias
3 states, ½ bias
static display
⅓ bias modes can drive 3.3 V LCDs.
½ bias and static modes can drive
both 3.3 V and 5 V LCDs.
LCD_ONLY
20A9[5]
0
0
W
Puts the part to sleep, but with the LCD display still active. LCD_ONLY is ignored if
system power is present. While in SLEEP mode, the device will wake up on reset,
when the autowake timer times out, when the push button is pushed, or when system
power returns.
2030[3:0]
…
2043[3:0]
0
…
0
L
…
L
R/W LCD Segment Data. Each word contains information for 1 to 4 time divisions of each
LCD_SEG0[3:0]
…
LCD_SEG19[3:0]
…
segment. Some addresses are used to address two segments.
R/W
In each word, bit 0 corresponds to COM0, bit 1 to COM1, bit 2 to COM2 and bit 3 to
COM3 of the first segment. Bits 4 through 7 correspond to COM0 to COM3, respec-
tively, of the second segment.
LCD_SEG24[3:0] 2048[3:0]
0
…
0
L
…
L
R/W
…
R/W
…
…
LCD_SEG31[3:0] 204F[3:0]
Care should be taken when writing to LCD_SEG locations since some of them control
DIO pins.
LCD_SEG32[3:0] 2050[3:0]
0
L
R/W
80
© 2005-2009 TERIDIAN Semiconductor Corporation
v1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
