Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
4
Firmware Interface
4.1
I/O RAM and SFR Map – Functional Order
Unused bits are labeled as “Not Used” and grayed out. These bits contain no memory and are read by the MPU as zero. Bits labeled as “Re-
served” may be in use and should not be changed from the values given in parentheses. This table lists only the SFR registers that are not ge-
neric 8051 SFR registers. Bits marked with † apply to the 71M6531D/F only, bits marked with ‡ apply to the 71M6532D/F only and should be 0 for
the other device.
Table 48: I/O RAM Map in Functional Order
Name
Addr
2000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Configuration:
CE0
EQU[2:0]
CE_E
CE10MHZ
Not Used
CE1
2001
2002
2003
2004
2005
2006
2007
209D
20A7
20A8
20A9
20AA
20AB
20AC
20AD
PRE_SAMPS[1:0]
Not Used
SUM_CYCLES[5:0]
CE2
CHOP_E[1:0]
RTM_E
WD_OVF
EX_RTC
Not Used
EX_XFR
COMP0
CONFIG0
CONFIG1
VERSION
CONFIG2
CE3
Not Used
PLL_OK
PLS_INV
Not Used
Not Used
Not Used
ECK_DIS
Not Used
CKOUT_E
M26MHZ
Not Used
VREF_DIS
ADC_E
Not Used
COMP_STAT
VREF_CAL
MPU_DIV[2:0]
Not Used
Not Used
MUX_ALT
M40MHZ
VERSION[7:0]
EX_FWCOL
OPT_TXE[1:0]
EX_PLL
FIR_LEN[1:0]
OPT_FDC[1:0]
Not Used
MUX_DIV[3:0]
CE4
BOOT_SIZE[7:0]
CE_LCTN[7:0]
Not Used
WAKE_RES
CE5
WAKE
WAKE_ARM
SLEEP
LCD_ONLY
WAKE_PRD[2:0]
SEL_IAN‡
TMUX
Not Used
TMUX[4:0]
ANACTRL
CONFIG3
CONFIG4
Reserved (0000)
SEL_IBN‡
Reserved (0) Reserved (0)
LCD_DAC[2:0]
CHOP_I_EN‡
CHOP_IA‡
Not Used
Not Used
CHOP_IB‡
Not Used
Not Used
Reserved (0) Reserved (0)
Interrupts and WD Timer:
INTBITS
IFLAGS
SFR F8
WD_RST
INT6
INT5
INT4
INT3
INT2
INT1
INT0
SFR E8 IE_PLLFALL IE_PLLRISE
IE_WAKE
IE_PB
IE_FWCOL1 IE_FWCOL0
IE_RTC
IE_XFER
Flash Memory:
ERASE
SFR 94
FLSH_ERASE[7:0]
FLSHCTL SFR B2
FL_BANK SFR B6
PREBOOT
SECURE
WRPROT_BT WRPROT_CE
Not Used
Not Used
FLSH_MEEN
FLBANK[2:0]
FLSH_PWE
PGADR
SFR B7
FLSH_PGADR[5:0]
Not Used
70
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