Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
71M6531
71M6531
V3P3SYS
V3P3SYS
VBAT
3.3V
3.3V
VBAT
LED
V3P3D
V3P3D
DIO1
DIO1
R
R
LED
DGND
DGND
Not recommended
Recommended
Figure 10: Connecting an External Load to DIO Pins
1.5.10 LCD Drivers – 71M6531D/F
The 71M6531 contains a total of 39 dedicated and multiplexed LCD drivers which are grouped as follows:
• 11 dedicated LCD segment drivers – always available
• 3 drivers multiplexed with the ICE interface (E_TCLK, E_RST, E_RXTX) – available in normal opera-
tion mode (when not emulating)
• 2 driver multiplexed with auxiliary signals MUX_SYNC and CKTEST (SEG7, SEG19) – available
when not used for test
• 4 drivers multiplexed with the SPI port (PCLK, PSDO, PCSZ, PSDI)
• 19 multi-use pins described above in the 1.5.7 Digital I/O – 71M6531D/F section.
• 4 common drivers for multiplexing (25%, 33%, 50%, or 100% duty cycle) – always available
With a minimum of 16 driver pins always available and a total of 39 driver pins in the maximum con-
figuration, the device is capable of driving between 64 to 156 pixels of LCD display with 25% duty cycle. At
eight pixels per digit, this corresponds to 8 to 19 digits. At 33% duty cycle, 48 to 117 pixels can be driven.
For each multi-use pin, the corresponding LCD_BITMAP[] register (as described in Section 1.5.7 Digital I/O
– 71M6531D/F) is used to select the pin for DIO or LCD operation. The mapping of the LCD_BITMAP[]
registers is specified in Section 4.1 (I/O RAM registers). The LCD drivers are supported by the four
common pins (COM0 – COM3).
1.5.11 LCD Drivers – 71M6532D/F
The 71M6532D/F contains a total of 67 dedicated and multiplexed LCD drivers, which are grouped as
follows:
• 15 dedicated LCD segment drivers (SEG0 to SEG2, SEG8, SEG12 - SEG18, SEG20 – SEG23)
• 4 drivers multiplexed with the SPI port (SEG3 to SEG6)
• 2 drivers multiplexed with MUX_SYNC (SEG7) or CKTEST (SEG19)
• 3 drivers multiplexed with the ICE interface (SEG9 to SEG11)
• 43 multi-use LCD/DIO pins described in Section 1.5.8 Digital I/O – 71M6532D/F.
With a minimum of 15 driver pins always available and a total of 67 driver pins in the maximum con-
figuration, the device is capable of driving between 60 to 268 pixels of an LCD display with 25% duty
cycle. At eight pixels per digit, this corresponds to 7.5 to 33.5 digits.
For each multi-use pin, the corresponding LCD_BITMAP[ ] register (as described in Section 1.5.8 Digital I/O
– 71M6532D/F) is used to select the pin for DIO or LCD operation. The mapping of the LCD_BITMAP[ ]
registers is specified in Section 4.1 I/O RAM and SFR Map – Functional Order. The LCD drivers are sup-
ported by the four common pins (COM0 – COM3).
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