Data Sheet 71M6531D/F-71M6532D/F
Table 58: CE Pulse Generation Parameters
FDS 6531/6532 005
CE Ad-
dress
Name
Default
Description
Kh = VMAX*IMAX*47.1132 / (In_8*WRATE*NACC*X) Wh/pulse. The
default value results in a Kh of 1.0 Wh/pulse when 2520 samples
are taken in each accumulation interval (and VMAX=600,
IMAX = 442 [for 400µΩ shunt], In_8 = 1, X = 6).
Maximum value = 215 -1.
WRATE
827
0x21
Watt pulse generator input (see DIO_PW bit). The output pulse
rate is: APULSEW * FS * 2-32 * WRATE * X * 2-14. This input is buf-
fered and can be loaded during a computation interval. The
change will take effect at the beginning of the next interval.
APULSEW
APULSER
APULSE2
APULSE3
0
0
0x41
0x42
0x43
0x44
0x38
VAR pulse generator input (see DIO_PV bit). The output pulse rate
is: APULSER * FS*2-32 * WRATE * X * 2-14. This input is buffered and
can be loaded during a computation interval. The change will take
effect at the beginning of the next interval.
Third pulse generator input (see DIO_PV bit). The output pulse
rate is: APULSE2 * FS*2-32 * WRATE * X * 2-14. This input is buffered
and can be loaded during a computation interval. The change will
take effect at the beginning of the next interval.
0
Fourth pulse generator input (see DIO_PV bit). The output pulse
rate is: APULSE3 * FS*2-32 * WRATE * X * 2-14. This input is buffered
and can be loaded during a computation interval. The change will
take effect at the beginning of the next interval.
0
Register for pulse width control of XPULSE and YPULSE. The max-
imum pulse width is (2*PULSEWIDTH+1)*(1/FS). The default value
will generate pulses of 10 ms width at FS = 2520.62 Hz.
PULSE
WIDTH
12
4.3.9 CE Calibration Parameters
Table 59 lists the parameters that are typically entered to effect calibration of meter accuracy.
Table 59: CE Calibration Parameters
CE Ad-
Name
Default
Description
dress
0x10
0x11
0x12
0x13
0x18
These constants control the gain of their respective channels. The
nominal value for each parameter is 214 = 16384. The gain of
each channel is directly proportional to its gain constant. Thus, if
the gain of the IA channel is 1% slow, CAL_IA should be scaled by
1/(1 – 0.01) and the resulting value is 16549.
CAL_IA
CAL_VA
CAL_IB
16384
16384
16384
16384
0
CAL_VB
PHADJ_A
These two constants control the CT phase compensation. No com-
pensation occurs when PHADJ_X = 0. As PHADJ_X is increased,
more compensation (lag) is introduced. Range: ± 215 – 1. If it is
desired to delay the current by the angle Φ, the equations are:
0.02229⋅TANΦ
0.1487 − 0.0131⋅TANΦ
PHADJ _ X = 220
at 60Hz
PHADJ_B
0
0
0x19
0x1F
0.0155⋅TANΦ
0.1241− 0.009695⋅TANΦ
This register contains the anchor or reference point for the tem-
perature measurement. At calibration temperature, the value read
at TEMP_RAW_X should be written to TEMP_NOM. The CE will
calculate the chip temperature TEMP_X relative to the reference
temperature.
PHADJ _ X = 220
at 50Hz
TEMP_NOM
The scale factor for the temperature calculation. It is not necessary
to use values other than the default value.
DEGSCALE
9174
0x39
92
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