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71M6531D-IMR/F 参数 Datasheet PDF下载

71M6531D-IMR/F图片预览
型号: 71M6531D-IMR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 电能计量IC [Energy Meter IC]
分类和应用: 电源电路电源管理电路
文件页数/大小: 115 页 / 2363 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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Data Sheet 71M6531D/F-71M6532D/F  
FDS 6531/6532 005  
Name  
Location  
Reset Wake  
Dir  
Description  
MUX_ALT  
2005[2]  
0
0
R/W The MPU asserts this bit when it wishes the MUX to perform ADC conversions on an  
alternate set of inputs.  
If CHOP_E is 00, MUX_ALT is automatically asserted once per sumcycle, when  
XFER_BUSY falls.  
MUX_DIV[3:0]  
MUX_SYNC_E  
OPT_FDC[1:0]  
209D[3:0]  
2020[7]  
0
0
0
0
0
0
R/W The number of states in the input multiplexer.  
R/W When set, SEG7 outputs MUX_SYNC. Otherwise, SEG7 is an LCD pin.  
R/W Selects the modulation duty cycle for OPT_TX.  
2007[1:0]  
OPT_FDC[1:0]  
Function  
50% Low  
25% Low  
12.5% Low  
6.25% Low  
00  
01  
10  
11  
OPT_RXDIS  
OPT_RXINV  
OPT_TXE[1:0]  
2008[5]  
2008[4]  
2007[7:6]  
0
0
0
0
R/W Configures OPT_RX to an analog input to the optical UART comparator or as a digital  
input/output, DIO1: 0 = OPT_RX, 1 = DIO1.  
R/W Inverts the result from the OPT_RX comparator when 1. Affects only the UART input.  
Has no effect when OPT_RX is used as a DIO input.  
00  
00  
R/W Configures the OPT_TX output pin.  
OPT_TXE[1:0]  
Function  
OPT_TX  
DIO2  
00  
01  
10  
11  
WPULSE  
RPULSE  
OPT_TXINV  
2008[0]  
2008[1]  
0
0
0
0
R/W Inverts OPT_TX when 1. This inversion occurs before modulation.  
OPT_TXMOD  
R/W Enables modulation of OPT_TX. When OPT_TXMOD is set, OPT_TX is modulated  
when it would otherwise have been zero. The modulation is applied after any inver-  
sion caused by OPT_TXINV.  
PLL_OK  
2003[6]  
0
0
R
Indicates that system power is present and the clock generation PLL is settled.  
PLS_MAXWIDTH 2080[7:0]  
FF  
FF  
R/W Determines the maximum width of the pulse (low going pulse).  
[7:0]  
The maximum pulse width is (2*PLS_MAXWIDTH + 1)*TI. Where TI is PLS_INTERVAL.  
If PLS_INTERVAL = 0, TI is the sample time (397 µs). If set to 255, pulse width control  
is disabled and pulses are output with a 50% duty cycle.  
PLS_INTERVAL 2081[7:0]  
[7:0]  
0
0
R/W For PULSE_W and PULSE_V only: If the FIFO is used, PLS_INTERVAL must be set to  
81. If PLS_INTERVAL = 0, the FIFO is not used and pulses are output as soon as the  
CE issues them.  
82  
© 2005-2009 TERIDIAN Semiconductor Corporation  
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