FDS 6531/6532 005
Data Sheet 71M6531D/F-71M6532D/F
DIO24 and higher do not have SFR registers for direction control. DIO40 and higher do not have SFR re-
gisters for data access. The direction control of these pins is achieved with the LCD_SEGn[3] registers
and data access is controlled with the LCD_SEGn[0] registers in I/O RAM.
DIO56 through DIO58 are dedicated DIO pins. They are controlled with DIO_DIR56[7] through
DIO_DIR58[7] and with DIO_56[4] through DIO_58[4] in I/O RAM.
1.5.9 Digital IO – Common Characteristics for 71M6531D/F and 71M6532D/F
On reset or power-up, all DIO pins are inputs until they are configured for the desired direction under
MPU control. The pin function can be configured by the I/O RAM registers LCD_BITMAPn. Setting
LCD_BITMAPn = 1 configures the pin for LCD, setting LCD_BITMAPn = 0 configures it for DIO. Once a
pin is configured as DIO, it can be configured independently as an input or output with the DIO_DIR bits
or the LCD_SEGn registers. Input and output data are written to or read from the pins using SFR registers
P0, P1, and P2.
DIO24 and higher do not have SFR registers for direction control. DIO41 and higher do not have SFR
registers for data access. The direction control of these pins is achieved with the LCD_SEGn[3] registers
and data access is controlled with the LCD_SEGn[0] registers in I/O RAM.
Since the control for DIO_24 through DIO_53 is shared with the control for LCD segments, the firmware
must take care not to disturb the DIO pins when accessing the LCD segments and vice versa. Usually,
this requires reading the I/O RAM register, applying a mask and writing back the modified byte.
Table 41: DIO_DIR Control Bit
Table 42: Selectable Controls using the
DIO_DIR Bits
DIO_R
Value
Resource Selected for DIO Pin
None
DIO_DIR [n]
0
1
0
1
2
3
4
5
6
7
DIO Pin n Function
Input
Output
Reserved
T0 (counter 0 clock)
T1 (counter 1 clock)
High priority I/O interrupt (INT0 rising)
Low priority I/O interrupt (INT1 rising)
High priority I/O interrupt (INT0 falling)
Low priority I/O interrupt (INT1 falling)
Additionally, if DIO6 and DIO7 are configured as DIO and defined as outputs, they can be used as dedi-
cated pulse outputs (WPULSE = DIO6, VARPULSE = DIO7) using the DIO_PW and DIO_PV registers. In
this case, DIO6 and DIO7 are under CE control. DIO4 and DIO5 can be configured to implement the
EEPROM Interface.
The PB pin is a dedicated digital input. In addition, if the optical UART is not used, OPT_TX and
OPT_RX can be configured as dedicated DIO pins, DIO1 and DIO2, respectively (see Section 1.5.6 Optical
Interface).
The internal control resources selectable for the DIO pins are listed in Table 42. If more than one input is
connected to the same resource, the resources are combined using a logical OR.
Tracking DIO pins configured as outputs is useful for pulse counting without external hardware.
Either the interrupts or the counter/timer clocks can be used to count pulses on the pulse outputs
or interrupts on the CE’s power failure output.
When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as shown in
Figure 10, right), not source it from V3P3D (as shown in Figure 10, left). This is due to the resis-
tance of the internal switch that connects V3P3D to either V3P3SYS or VBAT.
v1.2
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