Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
Interrupt Description
Interrupt Enable
Interrupt Flag
Name
Name
Location
Location
SFR E8[2]
SFR E8[6]
SFR E8[7]
SFR E8[5]
SFR E8[4]
IE_FWCOL1
IE_PLLRISE
IE_PLLFALL
IE_WAKE
IE_PB
FWCOL1 interrupt (INT 2)
PLL_OK rise interrupt (INT 4)
PLL_OK fall interrupt (INT 4)
AUTOWAKE flag
EX_PLL
2007[5]
PB flag
The AUTOWAKE and PB flag bits are shown in Table 31 because they behave similarly to interrupt flags,
even though they are not actually related to an interrupt. These bits are set by hardware when the MPU
wakes from a push button or wake timeout. The bits are reset by writing a zero. Note that the PB flag is
set whenever the PB is pushed, even if the part is already awake.
Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 32:
Table 32: Interrupt Priority Level Groups
Group
Group Members
0
1
External interrupt 0
Timer 0 interrupt
Serial channel 1 interrupt
–
–
External interrupt 2
–
–
–
–
2
3
4
5
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
–
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
Each group of interrupt sources can be programmed individually to one of four priority levels (as shown in
Table 33) by setting or clearing one bit in the SFR interrupt priority register IP0 and one in IP1(Table 34).
If requests of the same priority level are received simultaneously, an internal polling sequence as shown
in Table 35 determines which request is serviced first.
Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best
to set the interrupt priority registers only once during initialization before interrupts are enabled.
Table 33: Interrupt Priority Levels
IP1[x]
IP0[x]
Priority Level
Level 0 (lowest)
Level 1
0
0
1
1
0
1
0
1
Level 2
Level 3 (highest)
Table 34: Interrupt Priority Registers (IP0 and IP1)
Register
Address
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
IP0[0]
–
–
–
IP0
IP1
SFR 0xA9
SFR 0xB9
IP0[5]
IP1[5]
IP0[4]
IP1[4]
IP0[3]
IP1[3]
IP0[2]
IP1[2]
IP0[1]
IP1[1]
–
IP1[0]
34
© 2005-2009 TERIDIAN Semiconductor Corporation
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