71M6521DE/71M6521FE
Energy Meter IC
DATASHEET
JANUARY 2008
when a HALT instruction is executed. For proper operation, the code pass must be completed before the multiplexer cycle
ends (see System Timing Summary in the Functional Description Section).
The CE program must begin on a 1Kbyte boundary of the flash address. The I/O RAM register CE_LCTN[4:0] defines which
1KB boundary contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[4:0].
The CE DRAM can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time slots are
reserved for FIR, RTM, and MPU, respectively, to prevent bus contention for CE DRAM data access. Holding registers are
used to convert 8-bit wide MPU data to/from 32-bit wide CE DRAM data, and wait states are inserted as needed, depending on
the frequency of CKMPU.
The CE DRAM contains 128 32-bit words. The MPU can read and write the CE DRAM as the primary means of data commu-
nication between the two processors.
Table 2 shows the CE DRAM addresses allocated to analog inputs from the AFE.
ADDRESS (HEX)
NAME
DESCRIPTION
Phase A current
Phase A voltage
Phase B current
Phase B voltage
Not used
Not used
Temperature
Battery Voltage
00
01
02
03
04
05
06
07
IA
VA
IB
VB
-
-
TEMP
VBAT
Table 2: CE DRAM Locations for ADC Results
The CE of the 71M6521DE/FE is aided by support hardware that facilitates implementation of equations, pulse counters, and
accumulators. This support hardware is controlled through I/O RAM locations EQU (equation assist), DIO_PV and DIO_PW
(pulse count assist), and PRE_SAMPS and SUM_CYCLES (accumulation assist). PRE_SAMPS and SUM_CYCLES support a dual
level accumulation scheme where the first accumulator accumulates results from PRE_SAMPS samples and the second accu-
mulator accumulates up to SUM_CYCLES of the first accumulator results. The integration time for each energy output is
PRE_SAMPS * SUM_CYCLES/2520.6 (with MUX_DIV = 1). CE hardware issues the XFER_BUSY interrupt when the accumula-
tion is complete.
Meter Equations
Compute Engine (CE) firmware and hardware for residential meter configurations implement the equations listed in Table 3.
The register EQU (located in the I/O RAM) specifies the equation to be used based on the number of phases used for
metering.
Watt & VAR Formula
Description
EQU
Element 0
Element 1
1 element, 2W 1φ with neutral current sense
and tamper detection (VA connected to VB)
0
VA IA
VA IB
1
2
VA(IA-IB)/2
VA IA
N/A
VB IB
1 element, 3W 1φ
2 element, 4W 2φ
Table 3: Meter Equations.
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© 2005-2008 TERIDIAN Semiconductor Corporation
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