71M6521DE/71M6521FE
Energy Meter IC
DATASHEET
JANUARY 2008
would be to clear them with a bit operation. This is to be avoided. The hardware implements bit operations as a byte wide read-
modify-write hardware macro. If an interrupt occurs after the read, but before the write, its flag will be cleared unintentionally.
The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a zero in the location of the bit to
be cleared. The flag bits are configured in hardware to ignore ones written to them.
Interrupt Enable
Interrupt Flag
Interrupt Description
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
XFER_BUSY interrupt (int 6)
RTC_1SEC interrupt (int 6)
FWCOL0 interrupt (int 2)
FWCOL1 interrupt (int 2)
PLL_OK rise interrupt (int 4)
PLL_OK fall interrupt (int 4)
AUTOWAKE flag
NAME
LOCATION
NAME
LOCATION
EX0
EX1
EX2
EX3
EX4
SFR A8[[0]
SFR A8[2]
SFR B8[1]
SFR B8[2]
SFR B8[3]
SFR B8[4]
SFR B8[5]
2002[0]
IE0
IE1
SFR 88[1]
SFR 88[3]
SFR C0[1]
SFR C0[2]
SFR C0[3]
SFR C0[4]
SFR C0[5]
SFR E8[0]
SFR E8[1]
SFR E8[3]
SFR E8[2]
SFRE8[6]
SFRE8[7]
SFRE8[5]
SFRE8[4]
IEX2
IEX3
IEX4
IEX5
EX5
EX6
IEX6
EX_XFER
EX_RTC
IE_XFER
IE_RTC
IE_FWCOL0
IE_FWCOL1
IE_PLLRISE
IE_PLLFALL
IE_WAKE
IE_PB
2002[1]
EX_FWCOL
EX_PLL
2007[4]
2007[5]
PB flag
Table 47: Interrupt Enable and Flag Bits
The AUTOWAKE and PB flag bits are shown in Table 47 because they behave similarly to interrupt flags, even though they are
not actually related to an interrupt. These bits are set by hardware when the MPU wakes from a push button or wake timeout.
The bits are reset by writing a zero. Note that the PB flag is set whenever the PB is pushed, even if the part is already awake.
Each interrupt has its own flag bit, which is set by the interrupt hardware and is reset automatically by the MPU interrupt
handler (0 through 5). XFER_BUSY and RTC_1SEC, which are OR-ed together, have their own enable and flag bits in addition
to the interrupt 6 enable and flag bits (see Table 47), and these interrupts must be cleared by the MPU software.
When servicing the XFER_BUSY and RTC_1SEC interrupts, special care must be taken to avoid lock-up
conditions: If, for example, the XFER_BUSY interrupt is serviced, control must not return to the main program
without checking the RTC_1SEC flag. If this rule is ignored, a RTC_1SEC interrupt appearing during the
XFER_BUSY service routine will disable the processing of any XFER_BUSY or RTC_1SEC interrupt, since both
interrupts are edge-triggered (see the Software User’s Guide SUG652X).
The external interrupts are connected as shown in Table 47. The polarity of interrupts 2 and 3 is programmable in the MPU via
the I3FR and I2FR bits in T2CON. Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU
literature states that interrupts 4 through 6 are defined as rising edge sensitive. Thus, the hardware signals attached to
interrupts 5 and 6 are inverted to achieve the edge polarity shown in Table 47.
SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has
its own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5).
XFER_BUSY and RTC_1SEC, which are OR-ed together, have their own enable and flag bits in addition to the interrupt 6 enable
and flag bits (see Table 47), and these interrupts must be cleared by the MPU software.
v1.0
© 2005-2008 TERIDIAN Semiconductor Corporation
Page: 33 of 101
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
