71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
V3P3
Internal
2
1
WPULSE
OPT_TX
DIO2
B
MOD
DUTY
from OPT_TX UART
A
0
OPT_TXINV
EN
OPT_TXE[1:0]
OPT_TXMOD
OPT_FDC
2
OPT_TXMOD=1,
OPT_TXMOD=0
OPT_FDC=2 (25%)
A
A
B
B
1/38kHz
Figure 7: Optical Interface
Digital I/O
The device includes up to 14 pins of general purpose digital I/O. These pins are compatible with 5V inputs (no current-limiting
resistors are needed). Some are dual function that can alternatively be used as LCD drivers (DIO4-11, 14-17) and some share
functions with the optical port (DIO1, DIO2). On reset or power-up, all DIO pins are inputs until they are configured for the
desired direction under MPU control. The pins are configured by the DIO registers and by the five bits of the LCD_NUM
register (located in I/O RAM). Once declared as DIO, each pin can be configured independently as an input or output with the
DIO_DIRn bits. A 3-bit configuration word, DIO_Rx, can be used for certain pins, when configured as DIO, to individually assign
an internal resource such as an interrupt or a timer control. Table 53 lists the direction registers and configurability associated
with each group of DIO pins. Table 54 shows the configuration for a DIO pin through its associated bit in its DIO_DIR register.
Tables showing the relationship between LCD_NUM and the available segment/DIO pins can be found in the Applications
section and in the I/O RAM Description under LCD_NUM[4:0].
DIO
Pin number
PB
62 57
0
0
1
2
3
2
3
--
--
4
5
6
7
8
9
10 11 12 13 14 15
37 38 39 40 41 42 43 44
4
--
--
--
--
20 21
1
1
5
6
6
7
7
0
0
1
1
2
3
6
6
7
7
Data Register
DIO0=P0 (SFR 0x80)
--
DIO_DIR0 (SFR 0xA2)
DIO1=P1 (SFR 0x90)
-- --
DIO_DIR1 (SFR 0x91)
2
4
5
2
3
Direction Register
Internal Resources
Configurable
Y
Y
Y
--
Y
Y
Y
Y
Y
Y
Y
Y
-- --
--
--
DIO
16 17 18 19 20 21 22 23
Pin number
22 12
--
--
--
--
--
--
--
--
--
--
--
--
0
0
1
1
Data Register
DIO2=P2 (SFR 0xA0)
-- -- -- --
DIO_DIR2 (SFR 0xA1)
--
--
--
--
Direction Register
Internal Resources
Configurable
N
N
-- -- -- --
Table 53: Data/Direction Registers and Internal Resources for DIO Pin Groups
V1.0
© 2005-2008 TERIDIAN Semiconductor Corporation
Page: 39 of 97
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
