71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
External Interrupts
The 71M6521BE MPU allows seven external interrupts. These are connected as shown in Table 45. The direction of interrupts
2 and 3 is programmable in the MPU. Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU
literature states that interrupt 4 through 6 are defined as rising edge sensitive. Thus, the hardware signals attached to
interrupts 5 and 6 are inverted to achieve the edge polarity shown in Table 45.
External
Interrupt
Connection
Polarity
Flag Reset
0
1
2
3
4
5
6
Digital I/O High Priority
Digital I/O Low Priority
FWCOL0, FWCOL1
CE_BUSY
PLL_OK (rising), PLL_OK (falling)
EEPROM busy
see DIO_Rx
see DIO_Rx
falling
automatic
automatic
automatic
automatic
automatic
automatic
manual
falling
rising
falling
falling
XFER_BUSY
Table 45: External MPU Interrupts
FWCOLx interrupts occur when the CE collides with a flash write attempt. See the flash write description for more detail.
SFR (special function register) enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has
its own flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler. Note that XFER_BUSY,
FWCOL0, FWCOL1, PLLRISE, PLLFALL, have their own enable and flag bits in addition to the interrupt 6, 4, and 2 enable and
flag bits.
IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler. The other flags, IE_XFER
through IE_PB, are cleared by writing a zero to them. Since these bits are in a bit-addressable SFR byte, common practice
would be to clear them with a bit operation. This is to be avoided. The hardware implements bit operations as a byte wide read-
modify-write hardware macro. If an interrupt occurs after the read, but before the write, its flag will be cleared unintentionally.
The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a zero in the location of the bit to
be cleared. The flag bits are configured in hardware to ignore ones written to them.
Interrupt Enable
Interrupt Flag
Interrupt Description
External interrupt 0
Name
Location
Name
Location
EX0
EX1
EX2
EX3
EX4
SFR A8[[0]
SFR A8[2]
SFR B8[1]
SFR B8[2]
SFR B8[3]
SFR B8[4]
SFR B8[5]
2002[0]
IE0
IE1
SFR 88[1]
SFR 88[3]
SFR C0[1]
SFR C0[2]
SFR C0[3]
SFR C0[4]
SFR C0[5]
SFR E8[0]
SFR E8[3]
SFR E8[2]
SFRE8[6]
SFRE8[7]
SFRE8[5]
SFRE8[4]
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
XFER_BUSY interrupt (int 6)
FWCOL0 interrupt (int 2)
FWCOL1 interrupt (int 2)
PLL_OK rise interrupt (int 4)
PLL_OK fall interrupt (int 4)
AUTOWAKE flag
IEX2
IEX3
IEX4
IEX5
EX5
EX6
IEX6
EX_XFER
IE_XFER
IE_FWCOL0
IE_FWCOL1
IE_PLLRISE
IE_PLLFALL
IE_WAKE
IE_PB
EX_FWCOL
EX_PLL
2007[4]
2007[5]
PB flag
Table 46: Interrupt Enable and Flag Bits
V1.0
© 2005-2008 TERIDIAN Semiconductor Corporation
Page: 33 of 97
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