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71M6521BE-IGT/F 参数 Datasheet PDF下载

71M6521BE-IGT/F图片预览
型号: 71M6521BE-IGT/F
PDF下载: 下载PDF文件 查看货源
内容描述: 电能计量IC [Energy Meter IC]
分类和应用:
文件页数/大小: 97 页 / 1586 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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71M6521BE  
Energy Meter IC  
DATA SHEET  
JANUARY 2008  
CE Calculations  
The CE performs the precision computations necessary to accurately measure energy. These computations include offset  
cancellation, products, product smoothing, product summation, frequency detection, and sag detection. All data computed by  
the CE is dependent on the selected meter equation as given by EQU (in I/O RAM). However, for the 6521BE CE code, EQU is  
always 0.  
Watt Formula  
(WSUM)  
Element Input Mapping  
EQU  
W0SUM  
W1SUM  
I0SQSUM  
I1SQSUM  
VA IA (1 element, 2W 1φ)  
with tamper detection  
0
VA*IA  
VA*IB  
IA  
IB  
CESTATUS  
Since the CE_BUSY interrupt occurs at 2520.6Hz, it is desirable to minimize the computation required in the interrupt handler  
of the MPU. The MPU can read the CE status word at every CE_BUSY interrupt.  
CE  
Address  
Name  
Description  
0x11E8  
CESTATUS  
See description of CE status word below  
The CE Status Word is used for generating early warnings to the MPU. It contains sag warnings for VA as well as the F0 bit, a  
clock derived from the fundamental input frequency. CESTATUS provides information about the status of voltage and input AC  
signal frequency, which are useful for generating early power fail warnings, e.g. to initiate necessary data storage. CESTATUS  
represents the status flags for the preceding CE code pass (CE busy interrupt). Sag alarms are not remembered from one  
code pass to the next. The CE Status word is refreshed at every CE_BUSY interrupt.  
The significance of the bits in CESTATUS is shown in the table below:  
CESTATUS  
Name  
Description  
[bit]  
31-29  
Not Used  
These unused bits will always be zero.  
F0 is a square wave at the exact fundamental input frequency.  
Mains Signal  
28  
F0  
F0  
27  
26  
CREEP  
SAG_B  
Normally zero. Becomes one when creep logic has been applied to either WA or WB.  
Normally zero. These bits come one when the voltage in the respective channel remains  
below SAG_THR for SAG_CNT samples. Will not return to zero until the voltage rises above  
SAG_THR.  
25  
SAG_A  
24-0  
Not Used  
These unused bits will always be zero.  
V1.0  
© 2005-2008 TERIDIAN Semiconductor Corporation  
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