71M6521BE
Energy Meter IC
DATA SHEET
JANUARY 2008
On-Chip Resources
Oscillator
The 71M6521BE oscillator drives a standard 32.768kHz watch crystal. These crystals are accurate and do not require a high-
current oscillator circuit. The 71M6521BE oscillator has been designed specifically to handle these crystals and is compatible
with their high impedance and limited power handling capability.
PLL and Internal Clocks
Timing for the device is derived from the 32.768kHz oscillator output. On-chip timing functions include the MPU master clock
and the delta-sigma sample clock. In addition, the MPU has two general counter/timers (see MPU section).
The ADC master clock, CKADC, is generated by an on-chip PLL. It multiplies the oscillator output frequency (CK32) by 150.
The CE clock frequency is always CK32 * 150, or 4.9152MHz, where CK32 is the 32kHz clock. The MPU clock frequency is
determined by MPU_DIV and can be 4.9152MHz *2-MPU_DIV Hz where MPU_DIV varies from 0 to 7 (MPU_DIV is 0 on power-
up). This makes the MPU clock scalable from 4.9152MHz down to 38.4kHz. The circuit also generates a 2x MPU clock for use
by the emulator. This clock is not generated when ECK_DIS is asserted by the MPU.
The setting of MPU_DIV is maintained when the device transitions to BROWNOUT mode, but the time base in BROWNOUT
mode is 28,672Hz.
Temperature Sensor
The device includes an on-chip temperature sensor for determining the temperature of the bandgap reference. The MPU may
request an alternate multiplexer frame containing the temperature sensor output by asserting MUX_ALT. The primary use of
the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system (see
section titled “Temperature Compensation”).
Physical Memory
Flash Memory: The 71M6521 includes 8KB of on-chip flash memory. The flash memory primarily contains MPU and CE
program code. It also contains images of the CE DRAM, MPU RAM, and I/O RAM. On power-up, before enabling the CE, the
MPU copies these images to their respective locations.
Allocated flash space for the CE program cannot exceed 1024 words (2KB). The CE program must begin on a 1KB boundary
of the flash address. The CE_LCTN[4:0] word defines which 1KB boundary contains the CE code. Thus, the first CE instruction
is located at 1024*CE_LCTN[4:0]. The CE_LCTN[4:0] register must be set before the CE is enabled.
The flash memory is segmented into 512 byte individually erasable pages.
The CE engine cannot access its program memory when flash write occurs. Thus, the flash write procedure is to begin a
sequence of flash writes when CE_BUSY falls (CE_BUSY interrupt) and to make sure there is sufficient time to complete the
sequence before CE_BUSY rises again. The actual time for the flash write operation will depend on the exact number of cycles
required by the CE program. Typically (CE program is 512 instructions, mux frame is 13 CK32 cycles), there will be 200µs of
flash write time, enough for 4 bytes of flash write. If the CE code is shorter, there will be even more time.
Two interrupts warn of collisions between the 8051 firmware and the CE timing. If a flash write is attempted while the CE is
busy, the flash write will not execute and the FW_COL0 interrupt will be issued. If a flash write is still in progress when the CE
would otherwise begin a code pass, the code pass is skipped, the write is completed, and the FW_COL1 interrupt is issued.
The bit FLASH66Z (see I/O RAM table) defines the speed for accessing flash memory. To minimize supply current draw, this bit
should be set to 1.
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence. These special
pattern/sequence requirements prevent inadvertent erasure of the flash memory.
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