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71M6521BE-IGT/F 参数 Datasheet PDF下载

71M6521BE-IGT/F图片预览
型号: 71M6521BE-IGT/F
PDF下载: 下载PDF文件 查看货源
内容描述: 电能计量IC [Energy Meter IC]
分类和应用:
文件页数/大小: 97 页 / 1586 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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71M6521BE  
Energy Meter IC  
DATA SHEET  
JANUARY 2008  
When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 52. Once interrupt service has  
begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return from instruction,  
"RETI". When a RETI instruction is performed, the processor will return to the instruction that would have been next when the  
interrupt occurred.  
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless of  
whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, then samples are polled  
by the hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then the interrupt request flag is set.  
On the next instruction cycle, the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector  
address, if the following conditions are met:  
No interrupt of equal or higher priority is already in progress.  
An instruction is currently being executed and is not completed.  
The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.  
Special Function Registers for Interrupts:  
Interrupt Enable 0 register (IE0)  
MSB  
LSB  
EX0  
EAL  
WDT  
ES0  
ET1  
EX1  
ET0  
Table 34: The IEN0 Register  
Bit  
Symbol Function  
IEN0.7  
IEN0.6  
IEN0.5  
IEN0.4  
IEN0.3  
IEN0.2  
IEN0.1  
IEN0.0  
EAL  
WDT  
-
EAL=0 – disable all interrupts  
Not used for interrupt control  
ES0  
ET1  
EX1  
ET0  
EX0  
ES0=0 – disable serial channel 0 interrupt  
ET1=0 – disable timer 1 overflow interrupt  
EX1=0 – disable external interrupt 1  
ET0=0 – disable timer 0 overflow interrupt  
EX0=0 – disable external interrupt 0  
Table 35: The IEN0 Bit Functions  
Interrupt Enable 1 Register (IEN1)  
MSB  
LSB  
SWDT  
EX6  
EX5  
EX4  
EX3  
EX2  
Table 36: The IEN1 Register  
Page: 30 of 97  
© 2005-2008 TERIDIAN Semiconductor Corporation  
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